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| 型號： | AD5259EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5259 DGTL POT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5259 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5259BCPZ5-R7TR-ND - IC POT DGTL 5K 256POS 10LFCSP AD5259BCPZ50-R7TR-ND - IC POT DGTL 50K 256POS 10LFCSP AD5259BCPZ10-R7TR-ND - IC POT DGTL 10K 256POS 10LFCSP AD5259BCPZ100-R7TR-ND - IC POT DGTL 100K 256POS 10LFCSP AD5259BRMZ5-ND - IC POT DGTL 5K 256POS 10-MSOP AD5259BRMZ50-ND - IC POT DGTL 50K 256POS 10-MSOP AD5259BRMZ5-R7-ND - IC POT DGTL 5K 256POS 10MSOP AD5259BRMZ100-R7-ND - IC POT DGTL 100K 256POS 10MSOP AD5259BRMZ10-R7-ND - IC POT DGTL 10K 256POS 10MSOP AD5259BRMZ50-R7-ND - IC POT DGTL 50K 256POS 10MSOP 更多... |
Data Sheet
AD5259
Rev. C | Page 15 of 24
I2C-COMPATIBLE INTERFACE
The master initiates data transfer by establishing a start condi-
tion, which is when a high-to-low transition on the SDA line
occurs while SCL is high (see Figure 4). The next byte is the
slave address byte, which consists of the slave address (first
7 bits) followed by an R/W bit (see Table 6). When the R/W bit
is high, the master reads from the slave device. When the R/W
bit is low, the master writes to the slave device.
The slave address of the part is determined by two configurable
address pins, Pin AD0 and Pin AD1. The state of these two pins
is registered upon power-up and decoded into a corresponding
to the transmitted address bits responds by pulling the SDA
line low during the ninth clock pulse (this is termed the slave
acknowledge bit). At this stage, all other devices on the bus
remain idle while the selected device waits for data to be
written to, or read from, its serial register.
WRITING
In the write mode, the last bit (R/W) of the slave address byte is
logic low. The second byte is the instruction byte. The first three
bits of the instruction byte are the command bits (see Table 6).
The user must choose whether to write to the RDAC register,
EEPROM register, or activate the software write protect (see
Table 7 to Table 10). The final five bits are all zeros (see Table 13
to Table 14). The slave again responds by pulling the SDA line
low during the ninth clock pulse.
The final byte is the data byte MSB first. With the write protect
mode, data is not stored; rather, a logic high in the LSB enables
write protect. Likewise, a logic low disables write protect. The
slave again responds by pulling the SDA line low during the
ninth clock pulse.
STORING/RESTORING
In this mode, only the address and instruction bytes are
necessary. The last bit (R/W) of the address byte is logic
low. The first three bits of the instruction byte are the
command bits (see Table 6). The two choices are transfer
data from RDAC to EEPROM (store), or from EEPROM
to RDAC (restore). The final five bits are all zeros (see
Table 13 to Table 14). In addition, users should issue an
NOP command immediately after restoring the EEMEM
setting to RDAC, thereby minimizing supply current
dissipation.
READING
Assuming the register of interest was not just written to, it is
necessary to write a dummy address and instruction byte. The
instruction byte will vary depending on whether the data that
is wanted is the RDAC register, EEPROM register, or tolerance
register (see Table 11 and Table 16).
After the dummy address and instruction bytes are sent, a repeat
start is necessary. After the repeat start, another address byte is
needed, except this time the R/W bit is logic high. Following this
address byte is the readback byte containing the information
requested in the instruction byte. Read bits appear on the nega-
tive edges of the clock.
The tolerance register can be read back individually (see
Modes section for detailed information on the interpretation
of the tolerance bytes.
After all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a low-to-
high transition on the SDA line while SCL is high. In write mode,
the master pulls the SDA line high during the tenth clock pulse
to establish a stop condition (see Figure 46). In read mode, the
master issues a no acknowledge for the ninth clock pulse (that is,
the SDA line remains high). The master then brings the SDA line
low before the tenth clock pulse, and then raises SDA high to
establish a stop condition (see Figure 47).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowl-
edged its slave address and instruction bytes in the write mode,
the RDAC output is updated on each successive byte until a stop
condition is received. If different instructions are needed, the
write/read mode has to start again with a new slave address,
instruction, and data byte. Similarly, a repeated read function
of the RDAC is also allowed.
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