參數(shù)資料
型號: AD5302BRMZ
廠商: Analog Devices Inc
文件頁數(shù): 1/24頁
文件大小: 0K
描述: IC DAC 8BIT DUAL R-R 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
設(shè)置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 2.5mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs
AD5302/AD5312/AD5322
Rev. D
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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Tel: 781.329.4700
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2006-2011 Analog Devices, Inc. All rights reserved.
FEATURES
AD5302: Two 8-bit buffered DACs in 1 package
A version: ±1 LSB INL, B version: ±0.5 LSB INL
AD5312: Two 10-bit buffered DACs in 1 package
A version: ±4 LSB INL, B version: ±2 LSB INL
AD5322: Two 12-bit buffered DACs in 1 package
A version: ±16 LSB INL, B version: ±8 LSB INL
10-lead MSOP
Micropower operation: 300 μA @ 5 V (including
reference current)
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/Unbuffered reference input options
0 V to VREF output voltage
Power-on-reset to 0 V
Simultaneous update of DAC outputs via LDAC
Low power serial interface with Schmitt-triggered inputs
On-chip rail-to-rail output buffer amplifiers
Qualified for automotive applications
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail-
to-rail with a slew rate of 0.7 V/μs. The AD5302/AD5312/AD5322
utilize a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz and is compatible with standard SPI,
QSPI, MICROWIRE, and DSP interface standards.
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs can be configured as
buffered or unbuffered inputs. The outputs of both DACs can be
updated simultaneously using the asynchronous LDAC input.
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a power-
down feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides software-
selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated
equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW
at 3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
DAC
REGISTER
RESISTOR
NETWORK
POWER-DOWN
LOGIC
RESISTOR
NETWORK
BUFFER
STRING
DAC
STRING
DAC
AD5302/AD5312/AD5322
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
INTERFACE
LOGIC
SCLK
POWER-ON
RESET
VDD
VREFA
VOUTA
VOUTB
GND
VREFB
LDAC
DIN
00
92
8-
00
1
SYNC
BUFFER
Figure 1.
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