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參數(shù)資料
| 型號： | AD5302BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL R-R 10-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 設置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5302/AD5312/AD5322
Rev. D | Page 14 of 24
FUNCTIONAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. They contain reference buffers and output
buffer amplifiers, and are written to via a 3-wire serial interface.
They operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/μs. Each DAC is provided with a separate
reference input, which can be buffered to draw virtually no
current from the reference source, or unbuffered to give a
reference input range from GND to VDD. The devices have three
programmable power-down modes, in which one or both DACs
can be turned off completely with a high impedance output, or
the output can be pulled low by an on-chip resistor.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
N
REF
OUT
D
V
2
×
=
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0 to 255 for AD5302 (8 bits)
0 to 1023 for AD5312 (10 bits)
0 to 4095 for AD5322 (12 bits)
N = DAC resolution.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
OUTPUT BUFFER
AMPLIFIER
REFERENCE
BUFFER
SWITCH
CONTROLLED
BY CONTROL
LOGIC
VREFA
VOUTA
00928-
028
Figure 28. Single DAC Channel Architecture
RESISTOR STRING
The resistor-string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
TO OUTPUT
AMPLIFIER
00
92
8-
0
29
Figure 29. Resistor String
DAC REFERENCE INPUTS
There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as
unbuffered. The advantage of the buffered input is the high
impedance it presents to the voltage source driving it.
However, if the unbuffered mode is used, the user can have a
reference voltage as low as GND and as high as VDD because
there is no restriction due to headroom and footroom of the
reference amplifier. If there is a buffered reference in the circuit
(for example, REF192), there is no need to use the on-chip
buffers of the AD5302/AD5312/AD5322. In unbuffered mode,
the impedance is still large (180 kΩ per reference input).
The buffered/unbuffered option is controlled by the BUF bit in
the control word (see the Serial Interface section for a
description of the register contents).
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to VDD – 0.001 V when the reference is VDD.
It is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and VDD. The source and sink capabilities of the output
amplifier can be seen in Figure 16.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs. See Figure 21.
POWER-ON RESET
The AD5302/AD5312/AD5322 are provided with a power-on
reset function to power them up in a defined state. The power-
on state is
Normal operation
Reference inputs unbuffered
Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
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| AD5302BRMZ-REEL | 功能描述:IC DAC 8BIT DUAL R-R 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應商設備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD5302BRMZ-REEL7 | 功能描述:IC DAC 8BIT DUAL R-R 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5303 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| AD53032 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance Driver/Comparator Active Load on a Single Chip |
| AD53032JSTP | 制造商:Analog Devices 功能描述:High Performance Driver/Comparator 52-Pin LQFP |
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