參數(shù)資料
型號: AD5371BBCZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 1/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 40CH SER 100-CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 20µs
位數(shù): 14
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 40
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 40 電壓,單極;40 電壓,雙極
采樣率(每秒): *
其它名稱: AD5371BBCZ-REELDKR
40-Channel, 14-Bit,
Serial Input, Voltage Output DAC
AD5371
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007–2008 Analog Devices, Inc. All rights reserved.
FEATURES
40-channel DAC in 80-lead LQFP and 100-ball CSP_BGA
Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage span of 4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI/LVDS serial interface
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
14
AD5371
VREF0
SIGGND0
VREF2
SIGGND4
SIGGND3
SIGGND2
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT16
TO
VOUT39
LDAC
DVCC
VDD
VSS AGND DGND
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
BUFFER
GROUP 0
SPI/LVDS
SYNC
SCLK
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
STATE
MACHINE
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
DAC 7
OFFSET
DAC 0
BUFFER
OFS0
REGISTER
14
8
14
DAC 0
REGISTER
14
DAC 7
REGISTER
MU
X
2
MU
X
1
MU
X
1
MU
X
1
MU
X
1
TO
MUX2
A/B SELECT
REGISTER
CONTROL
REGISTER
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
14
X2A
REGISTER
X2B
REGISTER
14
MU
X
2
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
BUFFER
GROUP 1
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
DAC 7
OFFSET
DAC 1
DAC 0
BUFFER
OFS1
REGISTER
14
8
DAC 0
REGISTER
14
DAC 7
REGISTER
MU
X
2
TO
MUX2
A/B SELECT
REGISTER
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
14
MU
X
2
VREF2 SUPPLIES
GROUP 2 TO GROUP 4
SIGGND1
GROUP 2 TO GROUP 4
ARE SAME AS GROUP 1
X2A
REGISTER
X2B
REGISTER
14
X2A
REGISTER
X2B
REGISTER
14
X2A
REGISTER
X2B
REGISTER
14
SERIAL
INTERFACE
05
81
4-
0
01
Figure 1.
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