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參數(shù)資料
| 型號： | AD5371BBCZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 40CH SER 100-CSPBGA |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 40 電壓，單極；40 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5371BBCZ-REELDKR |
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AD5371
Rev. B | Page 22 of 28
SERIAL INTERFACE
The AD5371 contains two high speed serial interfaces: an SPI-
compatible interface operating at clock frequencies up to 50 MHz
(20 MHz for read operations) and an LVDS interface. To minimize
both the power consumption of the device and the on-chip digital
noise, the interface powers up fully only when the device is being
written to, that is, on the falling edge of SYNC.
SPI INTERFACE
The serial interface is 2.5 V LVTTL-compatible when operating
from a 2.5 V to 3.6 V DVCC supply. The SPI interface is selected
when the SPI/LVDS pin is held low. It is controlled by four pins,
as described in Table 11.
Table 11. Pins That Control the SPI Interface
Pin
Description
SYNC
Frame synchronization input
SDI
Serial data input pin
SCLK
Clocks data in and out of the device
SDO
Serial data output pin for data readback
When the SPI mode is used, the SYNC, SDI, and SCLK pins
should be connected to DGND either directly or by using pull-
down resistors.
LVDS INTERFACE
The LVDS interface uses the same input pins, with the same
designations, as the SPI interface; however, SDO is not used. In
addition, three other pins are provided for the complementary
signals needed for differential operation, as described in Table 12.
Table 12. Pins That Control the LVDS Interface
Pin
Description
SYNC
Differential frame synchronization signal
SYNC
Differential frame synchronization signal
(complement)
SDI
Differential serial data input
SDI
Differential serial data input (complement)
SCLK
Differential serial clock input
SCLK
Differential serial clock input (complement)
SPI WRITE MODE
The AD5371 allows writing of data via the serial interface to
every register directly accessible to the serial interface, that is,
all registers except the X2A, X2B, and DAC registers. The X2A
and X2B registers are updated when the user writes to the X1A,
X1B, M, or C register, and the DAC data registers are updated
by LDAC.
The serial word (see Table 13) is 24 bits long: 14 of these bits are
data bits; six bits are address bits; two bits are mode bits that
determine what is done with the data; and two bits are reserved.
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5371 by clock pulses applied to SCLK. The first falling
edge of SYNC starts the write cycle. At least 24 falling clock edges
must be applied to SCLK to clock in 24 bits of data before SYNC
is taken high again. If SYNC is taken high before the 24th falling
clock edge, the write operation is aborted.
If a continuous clock is used, SYNC must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5371. If more than 24 falling clock edges are applied before
SYNC is taken high again, the input data becomes corrupted. If
an externally gated clock of exactly 24 pulses is used, SYNC can
be taken high any time after the 24th falling clock edge.
The input register addressed is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
taken low again.
Table 13. Serial Word Bit Assignment
I23
I22
I21
I20
I19
I18
I17
I16
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
M1
M0
A5
A4
A3
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1 Bit I1 and Bit I0 are reserved for future use and should be set to 0 when writing the serial word. These bits read back as 0.
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| AD5371BSTZ | 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5371BSTZ-REEL | 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5372 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel, 16/14, Serial Input, Voltage-Output DACs |
| AD5372BCPZ | 制造商:Analog Devices 功能描述:DAC 32CH-CH RES-STRING 16BIT 56LFCSP EP - Trays |
| AD5372BCPZ-REEL7 | 制造商:Analog Devices 功能描述:DAC 32CH-CH RES-STRING 16BIT 56LFCSP EP - Tape and Reel |
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