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| 型號(hào)： | AD5371BBCZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CH SER 100-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類(lèi)型： | 40 電壓，單極；40 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱(chēng)： | AD5371BBCZ-REELDKR |
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AD5371
Rev. B | Page 17 of 28
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or the X1B input
register, depending on the setting of the A/B bit in the control
register. If the A/B bit is 0, data is written to the X1A register.
If the A/B bit is 1, data is written to the X1B register. Note that
this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a per-
channel basis so that some writes are to X1A registers and
some writes are to X1B registers.
MUX
DAC
REGISTER
MUX
X1A
REGISTER
X1B
REGISTER
M
REGISTER
C
REGISTER
X2A
REGISTER
X2B
REGISTER
05
81
4-
02
0
Figure 20. Data Registers Associated with Each DAC Channel
Each DAC channel also has a gain (M) register and an offset (C)
register that allow trimming out of the gain and offset errors of
the entire signal chain. Data from the X1A register is operated
on by a digital multiplier and adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.
Although Figure 20 shows a multiplier and adder for each
channel, there is only one multiplier and one adder in the device
shared among all channels. This has implications for the update
speed when several channels are updated simultaneously, as
described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or C
register with the A/B control bit set to 0, the X2A data is recal-
culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B, or to M or C
with A/B set to 1. The X2A and X2B registers are not readable
or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B select register associated with each group of
eight DACs. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the X2B
register (Bit 0 through Bit 7 control DAC 0 to DAC 7).
Note that because there are 40 bits in five registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B select registers to 0 or to 1.
LOAD DAC
All DACs in the AD5371 can be updated simultaneously by
taking LDAC low when each DAC register is updated from
either its X2A or X2B register, depending on the setting of the
A/B select registers. The DAC register is not readable or directly
writable by the user. LDAC can be permanently tied low, and
the DAC output is updated whenever new data appears in the
appropriate DAC register.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are
three 14-bit offset DACs, one for Group 0, one for Group 1, and
one for Group 2 to Group 4. These allow the output range of all
DACs connected to them to be offset within a defined range.
Thus, subject to the limitations of headroom, it is possible to set
the output range of Group 0, Group 1, or Group 2 to Group 4 to
be unipolar positive, unipolar negative, or bipolar, either symmet-
rical or asymmetrical about 0 V. The DACs in the AD5371 are
factory trimmed with the offset DACs set at their default values.
This results in optimum offset and gain performance for the
default output range and span.
When the output range is adjusted by changing the value of the
offset DAC, an extra offset is introduced due to the gain error of
the offset DAC. The amount of offset is dependent on the magni-
tude of the reference and how much the offset DAC deviates from
its default value. See the Specifications section for this offset. The
worst-case offset occurs when the offset DAC is at positive or
negative full scale. This value can be added to the offset present
in the main DAC channel to give an indication of the overall
offset for that channel. In most cases, the offset can be removed
by programming the C register of the channel with an appropriate
value. The extra offset caused by the offset DAC needs to be taken
into account only when the offset DAC is changed from its default
value. Figure 21 shows the allowable code range that can be
loaded
to the offset DAC, depending on the reference value used.
Thus,
for a 5 V reference, the offset DAC should not be
programmed
with a value greater than 8192 (0x2000).
0
4096
8192
12288
16383
OFFSET DAC CODE
0
1
2
3
4
V
R
E
F
(V
)
5
RESERVED
05
81
4-
0
21
Figure 21. Offset DAC Code Range
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| AD5371BSTZ | 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:* |
| AD5371BSTZ-REEL | 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:* |
| AD5372 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:32-Channel, 16/14, Serial Input, Voltage-Output DACs |
| AD5372BCPZ | 制造商:Analog Devices 功能描述:DAC 32CH-CH RES-STRING 16BIT 56LFCSP EP - Trays |
| AD5372BCPZ-REEL7 | 制造商:Analog Devices 功能描述:DAC 32CH-CH RES-STRING 16BIT 56LFCSP EP - Tape and Reel |
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