參數(shù)資料
型號： AD5371BBCZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 13/29頁
文件大?。?/td> 0K
描述： IC DAC 14BIT 40CH SER 100-CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時間： 20µs
位數(shù)： 14
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 40
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 40 電壓，單極；40 電壓，雙極
采樣率（每秒）： *
其它名稱： AD5371BBCZ-REELDKR
AD5371
Rev. B | Page 19 of 28
Reference Selection Example
If
Nominal output range = 12 V (4 V to +8 V)
Zero-scale error = ±70 mV
Gain error = ±3%, and
SIGGNDx = AGND = 0 V
Then
Gain error = ±3%
=> Maximum positive gain error = 3%
=> Output range including gain error = 12 + 0.03(12) = 12.36 V
Zero-scale error = ±70 mV
=> Maximum offset error span = 2(70 mV) = 0.14 V
=> Output range including gain error and zero-scale error =
12.36 V + 0.14 V = 12.5 V
VREF calculation
Actual output range = 12.5 V, that is, 4.25 V to +8.25 V;
VREF = (8.25 V + 4.25 V)/4 = 3.125 V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference
level but can reduce the performance by overcompaction of
the transfer function.
Use a combination of these two approaches.
CALIBRATION
The user can perform a system calibration on the AD5371 to
reduce gain and offset errors to below 1 LSB. This reduction is
achieved by calculating new values for the M and C registers and
reprogramming them.
The M and C registers should not be programmed until both
the zero-scale and full-scale errors are calculated.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
1.
Set the output to the lowest possible value.
2.
Measure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
3.
Calculate the number of LSBs equivalent to the error and
add this number to the default value of the C register. Note
that only negative zero-scale error can be reduced.
Reducing Full-Scale Error
Full-scale error can be reduced as follows:
1.
Measure the zero-scale error.
2.
Set the output to the highest possible value.
3.
Measure the actual output voltage and compare it to the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
4.
Calculate the number of LSBs equivalent to the span error
and subtract this number from the default value of the M
register. Note that only positive full-scale error can be
reduced.
AD5371 Calibration Example
This example assumes that a 4 V to +8 V output is required.
The DAC output is set to 4 V but measured at 4.03 V. This
gives a zero-scale error of 30 mV.
1 LSB = 12 V/16,384 = 732.42 μV
30 mV = 41 LSBs
The full-scale error can now be calculated. The output is set to
8 V and a value of 8.02 V is measured. This gives a full-scale
error of +20 mV and a span error of +20 mV (30 mV) =
+50 mV.
50 mV = 68 LSBs
The errors can now be removed as follows:
1.
Add 41 LSBs to the default C register value:
8192 + 41 = 8233
2.
Subtract 68 LSBs from the default M register value:
16,383 68 = 16,315
3.
Program the M register to 16,315; program the C register
to 8233.
ADDITIONAL CALIBRATION
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently reduced. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
These limitations can be overcome by increasing the reference
value. With a 3 V reference, a 12 V span is achieved. The ideal
voltage range for the AD5371 is 4 V to +8 V. Using a +3.1 V
reference increases the range to 4.133 V to +8.2667 V. Clearly,
in this case, the offset and gain errors are insignificant, and the
M and C registers can be used to raise the negative voltage to
4 V and then reduce the maximum voltage to +8 V to give the
most accurate values possible.
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參數(shù)描述
AD5371BSTZ 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD5371BSTZ-REEL 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD5372 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel, 16/14, Serial Input, Voltage-Output DACs
AD5372BCPZ 制造商:Analog Devices 功能描述:DAC 32CH-CH RES-STRING 16BIT 56LFCSP EP - Trays
AD5372BCPZ-REEL7 制造商:Analog Devices 功能描述:DAC 32CH-CH RES-STRING 16BIT 56LFCSP EP - Tape and Reel
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