參數(shù)資料
型號(hào)： AD5373BSTZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 32CH SER 64-LQFP
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 20µs
位數(shù)： 14
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 250mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（14x14）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 32 電壓，單極；32 電壓，雙極
采樣率（每秒）： *
其它名稱： AD5373BSTZ-REELDKR
AD5372/AD5373
Rev. C | Page 19 of 28
ADDITIONAL CALIBRATION
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently reduced. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
These limitations can be overcome by increasing the reference
value. With a 3 V reference, a 12 V span is achieved. The ideal
voltage range, for the AD5372 or the AD5373, is 4 V to +8 V.
Using a +3.1 V reference increases the range to 4.133 V to
+8.2667 V. Clearly, in this case, the offset and gain errors are
insignificant, and the M and C registers can be used to raise
the negative voltage to 4 V and then reduce the maximum
voltage to +8 V to give the most accurate values possible.
RESET FUNCTION
The reset function is initiated by the RESET pin. On the rising
edge of RESET, the AD5372/AD5373 state machine initiates a
reset sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recom-
mended that the user bring RESET high as soon as possible to
properly initialize the registers.
When the reset sequence is complete (and provided that CLR is
high), the DAC output is at a potential specified by the default
register settings, which is equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and LDAC is taken low. The AD5372/AD5373 can be
returned to the default state by pulsing RESET low for at least
30 ns. Note that, because the reset function is triggered by the
rising edge, bringing RESET low has no effect on the operation
of the AD5372/AD5373.
CLEAR FUNCTION
CLR is an active low input that should be high for normal opera-
tion. The CLR pin has an internal 500 kΩ pull-down resistor.
When CLR is low, the input to each of the DAC output buffer
stages (VOUT0 to VOUT31) is switched to the externally set
potential on the relevant SIGGNDx pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the
DAC outputs return to their previous values. The contents of the
input registers and DAC Register 0 to DAC Register 31 are not
affected by taking CLR low. To prevent glitches from appearing
on the outputs, CLR should be brought low whenever the output
span is adjusted by writing to the offset DAC.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the BUSY output goes low. While
BUSY is low, the user can continue writing new data to the X1,
M, or C register (see the
section for more
details), but no DAC output updates can take place.
The BUSY pin is bidirectional and has a 50 kΩ internal pull-up
resistor. When multiple AD5372 or AD5373 devices are used in
one system, the BUSY pins can be tied together. This is useful
when it is required that no DAC in any device be updated until
all other DACs are ready. When each device has finished updating
the X2 (A or B) registers, it releases the BUSY pin. If another
device has not finished updating its X2 registers, it holds BUSY
low, thus delaying the effect of LDAC going low.
The DAC outputs are updated by taking the LDAC input low. If
LDAC goes low while BUSY is active, the LDAC event is stored
and the DAC outputs are updated immediately after BUSY goes
high. A user can also hold the LDAC input permanently low. In
this case, the DAC outputs are updated immediately after BUSY
goes high. Whenever the A/B select registers are written to, BUSY
also goes low, for approximately 500 ns.
The AD5372/AD5373 have flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in Group 0 to Group 3, the same channel in
Group 1 to Group 3, or all channels in the device. This means
that 1, 4, 8, or 32 DAC register values may need to be calculated
and updated. Because there is only one multiplier shared among
32 channels, this task must be done sequentially so that the
length of the BUSY pulse varies according to the number of
channels being updated.
Table 9. BUSY Pulse Widths
Action
BUSY Pulse Width1
Loading input, C, or M to 1 channel2
1.5 μs maximum
Loading input, C, or M to 4 channels
3.3 μs maximum
Loading input, C, or M to 8 channels
5.7 μs maximum
Loading input, C, or M to 32 channels
20.1 μs maximum
1
BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns.
2 A single channel update is typically 1 μs.
The AD5372/AD5373 contain an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
written to since the last time LDAC was brought low. Normally,
when LDAC is brought low, the DAC registers are filled with the
contents of the X2A or X2B register, depending on the setting of
the A/B select registers. However, the AD5372/AD5373 update
the DAC register only if the X2A or X2B data has changed,
thereby removing unnecessary digital crosstalk.
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