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| 型號： | AD5373BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH SER 64-LQFP |
| 標準包裝： | 1 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 250mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（14x14） |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 32 電壓，單極；32 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5373BSTZ-REELDKR |
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AD5372/AD5373
Rev. C | Page 16 of 28
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or the X1B input
register, depending on the setting of the A/B bit in the control
register. If the A/B bit is 0, data is written to the X1A register.
If the A/B bit is 1, data is written to the X1B register. Note that
this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a per-
channel basis so that some writes are to X1A registers and
some writes are to X1B registers.
05
81
5-
0
18
MUX
DAC
REGISTER
MUX
X1A
REGISTER
X1B
REGISTER
M
REGISTER
C
REGISTER
X2A
REGISTER
X2B
REGISTER
Figure 19. Data Registers Associated with Each DAC Channel
Each DAC channel also has a gain (M) register and an offset
(C) register, which allow trimming out of the gain and offset
errors of the entire signal chain. Data from the X1A register is
operated on by a digital multiplier and adder controlled by the
contents of the M and C registers. The calibrated DAC data is
then stored in the X2A register. Similarly, data from the X1B
register is operated on by the multiplier and adder and stored in
the X2B register.
Although a multiplier and adder symbol are shown in Figure 19
for each channel, there is only one multiplier and one adder in the
device, which are shared among all channels. This has implica-
tions for the update speed when several channels are updated at
once, as described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or
C register with the A/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B,
or to M or C with A/B set to 1. The X2A and X2B registers
are not readable or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or from the X2B register is
controlled by an 8-bit A/B select register associated with each
group of eight DACs. If a bit in this register is 0, the DAC takes
its data from the X2A register; if 1, the DAC takes its data from
the X2B register (Bit 0 through Bit 7 control DAC 0 to DAC 7).
Note that because there are 32 bits in four registers, it is possible to
set up, on a per-channel basis, whether each DAC takes its data
from the X2A or X2B register. A global command is also provided
that sets all bits in the A/B select registers to 0 or to 1.
LOAD DAC
All DACs in the AD5372/AD5373 can be updated simultane-
ously by taking LDAC low when each DAC register is updated
from either its X2A or X2B register, depending on the setting
of the A/B select registers. The DAC register is not readable or
directly writable by the user. LDAC can be permanently tied
low, and the DAC output is updated whenever new data appears
in the appropriate DAC register.
OFFSET DACs
In addition to the gain and offset trim for each DAC, there are
two 14-bit offset DACs, one for Group 0 and one for Group 1 to
Group 3. These allow the output range of all DACs connected to
them to be offset within a defined range. Thus, subject to the
limitations of headroom, it is possible to set the output range of
Group 0 or Group 1 to Group 3 to be unipolar positive, unipolar
negative, or bipolar, either symmetrical or asymmetrical about
0 V. The DACs in the AD5372/AD5373 are factory trimmed with
the offset DACs set at their default values. This gives the best offset
and gain performance for the default output range and span.
When the output range is adjusted by changing the value of the
offset DAC, an extra offset is introduced due to the gain error of
the offset DAC. The amount of offset is dependent on the
magnitude of the reference and how much the offset DAC
moves from its default value. See the Specifications section for
this offset. The worst-case offset occurs when the offset DAC is
at positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can
be removed by programming the C register of the channel with
an appropriate value. The extra offset caused by the offset DAC
needs to be taken into account only when the offset DAC is
changed from its default value. Figure 20 shows the allowable
code range that can be loaded to the offset DAC, depending on
the reference value used. Thus, for a 5 V reference, the offset
DAC should not be programmed with a value greater than 8192
(0x2000).
5
0
16383
0
581
5-
0
19
OFFSET DAC CODE
VR
E
F
(
V)
4
3
2
1
4096
8192
12288
RESERVED
Figure 20. Offset DAC Code Range
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