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參數(shù)資料
| 型號： | AD5373BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH SER 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 250mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（14x14） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 32 電壓，單極；32 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5373BSTZ-REELDKR |
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AD5372/AD5373
Rev. C | Page 24 of 28
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit boards on
which the AD5372/AD5373 are mounted should be designed
so that the analog and digital sections are separated and con-
fined to certain areas of the board. If the AD5372/AD5373 are
in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (VSS, VDD, DVCC),
it is recommended that these pins be tied together and that each
supply be decoupled only once.
The AD5372/AD5373 should have ample supply decoupling of
10 μF in parallel with 0.1 μF on each supply located as close to
the package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI)—typical of the common ceramic types
that provide a low impedance path to ground at high frequencies—
to handle transient currents due to internal logic switching.
Digital lines running under the device should be avoided because
they can couple noise onto the device. The analog ground plane
should be allowed to run under the AD5372/AD5373 to avoid
noise coupling. The power supply lines of the AD5372/AD5373
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast switching digital signals should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
they should never be run near the reference inputs. It is essential
to minimize noise on the VREF0 and VREF1 lines.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to
each other. This reduces the effects of feedthrough through
the board. A microstrip technique is by far the best approach,
but it is not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground plane, while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5372/AD5373, it is
important that the AGND and DGND pins be connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications, this is not an issue because the
ground pins for the power supplies are connected to the ground
pins of the AD5372/AD5373 via ground planes. When the
AD5372/AD5373 are to be used in a hot-swap card, care should
be taken to ensure that the ground pins are connected to the
supply grounds before the positive or negative supplies are
connected. This is required to prevent currents from flowing
in directions other than toward an analog or digital ground.
INTERFACING EXAMPLES
The SPI interface of the AD5372/AD5373 is designed to allow
the parts to be easily connected to industry-standard DSPs and
microcontrollers. Figure 22 shows how the AD5372/AD5373
connects to the Analog Devices, Inc., Blackfin DSP. The Blackfin
has an integrated SPI port that can be connected directly to the
SPI pins of the AD5372/AD5373 and programmable I/O pins
that can be used to set or read the state of the digital input or
output pins associated with the interface.
05
81
5-
02
1
SPISELx
ADSP-BF531
AD5372/
AD5373
SCK
MOSI
MISO
PF10
PF8
PF9
PF7
SYNC
SCLK
SDI
SDO
RESET
CLR
LDAC
BUSY
Figure 22. Interfacing to a Blackfin DSP
The Analog Devices ADSP-21065L is a floating-point DSP with
two serial ports (SPORTs). Figure 23 shows how one SPORT can
be used to control the AD5372/AD5373. In this example, the
transmit frame synchronization (TFSx) pin is connected to the
receive frame synchronization (RFSx) pin. Similarly, the transmit
and receive clocks (TCLKx and RCLKx) are also connected. The
user can write to the AD5372/AD5373 by writing to the transmit
register of the ADSP-21065L. A read operation can be accom-
plished by first writing to the AD5372/AD5373 to tell the part
that a read operation is required. A second write operation with
an NOP instruction causes the data to be read from the
AD5372/AD5373. The DSP receive interrupt can be used to
indicate when the read operation is complete.
05
81
5-
02
2
SYNC
SCLK
SDI
SDO
RESET
CLR
LDAC
BUSY
AD5372/
AD5373
ADSP-21065L
TFSx
RFSx
TCLKx
RCLKx
DTxA
DRxA
FLAG0
FLAG1
FLAG2
FLAG3
Figure 23. Interfacing to an ADSP-21065L DSP
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