- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1978 > AD5378ABC (Analog Devices Inc)IC DAC 14BIT 32CHAN 108CSPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | AD5378ABC |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 32CHAN 108CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 850mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 108-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 108-CSPBGA（13x13） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，雙極 |
| 采樣率（每秒）： | 50k |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
AD5378
Rev. A | Page 19 of 28
VBIAS FUNCTION
The AD5378 on-chip voltage generator provides a bias voltage
of 4.25 V (min). The VBIAS pin is provided for bypassing and
overdriving purposes only. It is not intended to be used as a
supply or a reference. If VREF(+) > 4.25 V, VBIAS must be pulled
high externally to an equal or higher potential such as 5 V. The
external voltage source should be capable of driving a 50 μA
(typical) current sink load.
REFERENCE SELECTION
The voltages applied to VREF(+) and VREF() determine the
output voltage range and span on VOUT0 to VOUT31. If the
offset and gain features are not used (m and c are left at their
power-on values), the reference levels required can be
calculated as follows:
VREF(+)min = (VOUTmax VOUTmin)/3.5
VREF()max = (AGND + VOUTmin)/2.5
If the offset and gain features of the AD5378 are used, the
output range required is slightly different. The output range
chosen should take into account the offset and gain errors that
need to be trimmed out. Therefore, the output range should be
larger than the actual required range.
The reference levels required can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
3.
Calculate the new maximum output range on VOUT,
including the maximum offset and gain errors expected.
4.
Choose the new VOUTmax and VOUTmin required, keeping
the new VOUT limits centered on the nominal values and
assuming REFGND is 0 V (or equal to AGND). VDD and
VSS must provide sufficient headroom.
5.
Calculate the values of VREF(+) and VREF() as follows:
VREF(+)min = (VOUTmax VOUTmin)/3.5
VREF()max = (AGND + VOUTmin)/2.5
In addition, when using reference values other than those
suggested (VREF(+) = 5 V and VREF() = 3.5 V), the expected
offset error component changes as follows:
VOFFSET = 0.125 × (VREF()A + 0.7 × VREF(+)A)
where:
VREF()A is the new negative reference value.
VREF(+)A is the new positive reference value.
If this offset error too large to calibrated out, it is possible to
adjust the negative reference value to account for this by using
the following equation:
VREF()NEW = VREF()A VOFFSET/2.625
Reference Selection Example
Nominal Output Range = 10 V; (2 V to +8 V)
Offset Error = ±100 mV
Gain Error = ±3%
REFGND = AGND = 0 V
1.
Gain Error = ±3%;
=> Maximum Positive Gain Error = +3%
=> Output Range including Gain Error =
10 + 0.03 (10) = 10.3 V
2.
Offset Error = ±100 mV;
=> Maximum Offset Error Span = 2(100) mV = 0.2 V
=> Output Range including Gain Error and Offset Error =
10.3 + 0.2 = 10.5 V
3.
VREF(+) and VREF() Calculation:
Actual Output Range = 10.5 V, that is, 2.25 V to +8.25 V
(centered);
=> VREF(+) = (8.25 + 2.25)/3.5 = 3 V and
VREF() = 2.25/2.5 = 0.9 V
If the solution yields inconvenient reference levels, the user can
adopt one of these approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select convenient reference levels above VREF(+)min or below
VREF()max. Modify the gain and offset registers to downsize
the references digitally. In this way, the user can use almost
any convenient reference level, but can reduce performance
by overcompaction of the transfer function.
Use a combination of these two approaches.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5379ABC | IC DAC 14BIT 40CH 108-CSPBGA |
| AD5380BSTZ-3 | IC DAC 14BIT 40CHAN 3V 100LQFP |
| AD5381BSTZ-5 | IC DAC 12BIT 40CH 5V 100-LQFP |
| AD5382BSTZ-3 | IC DAC 14BIT 32CHAN 3V 100LQFP |
| AD5390BCPZ-5 | IC DAC 14BIT 16CHAN 5V 64LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5378ABCZ | 功能描述:IC DAC 14BIT 32CHAN 108CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5378ABCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC |
| AD5379 | 制造商:AD 制造商全稱:Analog Devices 功能描述:40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC |
| AD5379ABC | 功能描述:IC DAC 14BIT 40CH 108-CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5379ABCZ | 功能描述:IC DAC 14BIT 40CHAN 108CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。