參數(shù)資料
型號: AD5378ABC
廠商: Analog Devices Inc
文件頁數(shù): 24/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CHAN 108CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 850mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 108-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 108-CSPBGA(13x13)
包裝: 托盤
輸出數(shù)目和類型: 32 電壓,雙極
采樣率(每秒): 50k
AD5378
Rev. A | Page 3 of 28
GENERAL DESCRIPTION
The AD5378 contains 32 14-bit DACs in one CSPBGA package.
The AD5378 provides a bipolar output range determined by the
voltages applied to the VREF(+) and VREF() inputs. The maximum
output voltage span is 17.5 V, corresponding to a bipolar output
range of 8.75 V to +8.75 V, and is achieved with reference volt-
ages of VREF() = 3.5 V and VREF(+) = +5 V.
The AD5378 guarantees operation over a wide VSS/VDD supply
range from ±11.4 V to ±16.5 V. The output amplifier headroom
requirement is 2.5 V operating with a load current of 1.5 mA,
and 2 V operating with a load current of 0.5 mA.
The AD5378 contains a double-buffered parallel interface in
which 14 data bits are loaded into one of the input registers
under the control of the WR, CS, and DAC channel address
pins, A0 to A7. It also has a 3-wire serial interface, which is
compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards and can handle clock speeds of up to 50 MHz.
The DAC outputs are updated when the DAC registers receive
new data. All the outputs can be updated simultaneously by
taking the LDAC input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external REFGND input. The DAC outputs can also be
switched to REFGND via the CLR pin. Table 1 and Table 2
show the product portfolio for high channel count bipolar and
unipolar voltage output DACs.
Table 1. 40-Channel, Bipolar, Voltage Output DAC
Model
Resolution
Analog Supplies
Output
Channels
Linearity Error (LSB)
Package
Description
Package Option
AD5379ABC
14 Bits
±11.4 V to ±16.5 V
40
±3
108-Lead CSPBGA
BC-108
Table 2. High Channel Count, Low Voltage, Single-Supply DACs
Model
Resolution
AVDD Range
Output
Channels
Linearity Error (LSB)
Package
Description
Package Option
AD5380BST-5
14 Bits
4.5 V to 5.5 V
40
±4
100-Lead LQFP
ST-100
AD5380BST-3
14 Bits
2.7 V to 3.6 V
40
±4
100-Lead LQFP
ST-100
AD5381BST-5
12 Bits
4.5 V to 5.5 V
40
±1
100-Lead LQFP
ST-100
AD5381BST-3
12 Bits
2.7 V to 3.6 V
40
±1
100-Lead LQFP
ST-100
AD5384BBC-5
14 Bits
4.5 V to 5.5 V
40
±4
100-Lead CSPBGA
BC-100
AD5384BBC-3
14 Bits
2.7 V to 3.6 V
40
±4
100-Lead CSPBGA
BC-100
AD5382BST-5
14 Bits
4.5 V to 5.5 V
32
±4
100-Lead LQFP
ST-100
AD5382BST-3
14 Bits
2.7 V to 3.6 V
32
±4
100-Lead LQFP
ST-100
AD5383BST-5
12 Bits
4.5 V to 5.5 V
32
±1
100-Lead LQFP
ST-100
AD5383BST-3
12 Bits
2.7 V to 3.6 V
32
±1
100-Lead LQFP
ST-100
AD5390BST-5
14 Bits
4.5 V to 5.5 V
16
±3
52-Lead LQFP
ST-52
AD5390BCP-5
14 Bits
4.5 V to 5.5 V
16
±3
64-Lead LFCSP
CP-64
AD5390BST-3
14 Bits
2.7 V to 3.6 V
16
±4
52-Lead LQFP
ST-52
AD5390BCP-3
14 Bits
2.7 V to 3.6 V
16
±4
64-Lead LFCSP
CP-64
AD5391BST-5
12 Bits
4.5 V to 5.5 V
16
±1
52-Lead LQFP
ST-52
AD5391BCP-5
12 Bits
4.5 V to 5.5 V
16
±1
64-Lead LFCSP
CP-64
AD5391BST-3
12 Bits
2.7 V to 3.6 V
16
±1
52-Lead LQFP
ST-52
AD5391BCP-3
12 Bits
2.7 V to 3.6 V
16
±1
64-Lead LFCSP
CP-64
AD5392BST-5
14 Bits
4.5 V to 5.5 V
8
±3
52-Lead LQFP
ST-52
AD5392BCP-5
14 Bits
4.5 V to 5.5 V
8
±3
64-Lead LFCSP
CP-64
AD5392BST-3
14 Bits
2.7 V to 3.6 V
8
±4
52-Lead LQFP
ST-52
AD5392BCP-3
14 Bits
2.7 V to 3.6 V
8
±4
64-Lead LFCSP
CP-64
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