參數(shù)資料
型號(hào): AD5410AREZ
廠商: Analog Devices Inc
文件頁數(shù): 14/32頁
文件大小: 0K
描述: IC DAC 12BIT 1CH SER 24TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
Weigh Scale Introduction
設(shè)計(jì)資源: Simplified 12-Bit, 4 mA-to-20 mA Output Solution Using AD5410 (CN0081)
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 40µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極
采樣率(每秒): *
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
Data Sheet
AD5410/AD5420
Rev. F | Page 21 of 32
RESET REGISTER
The reset register is addressed by setting the address byte of the
input shift register to 0x56. The reset register contains a single
reset bit at Position DB0, as shown in Table 16. Writing a logic
high to this bit performs a reset operation, restoring the part to
its power-on state.
STATUS REGISTER
The status register is a read-only register. The status register bit
functionality is shown in Table 15 and Table 17.
Table 15. Status Register Bit Functions
Bit
Description
IOUT Fault
This bit is set if a fault is detected on the IOUT pin.
Slew Active
This bit is set while the output value is slewing
(slew rate control enabled).
Overtemp
This bit is set if the AD5410/AD5420 core
temperature exceeds approximately 150°C.
Table 16. Programming the Reset Register
MSB
LSB
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Reserved
Reset
Table 17. Decoding the Status Register
MSB
LSB
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Reserved
IOUT fault
Slew active
Overtemp
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