參數(shù)資料
型號: AD5410AREZ
廠商: Analog Devices Inc
文件頁數(shù): 4/32頁
文件大?。?/td> 0K
描述: IC DAC 12BIT 1CH SER 24TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
Weigh Scale Introduction
設(shè)計資源: Simplified 12-Bit, 4 mA-to-20 mA Output Solution Using AD5410 (CN0081)
標(biāo)準(zhǔn)包裝: 62
設(shè)置時間: 40µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極
采樣率(每秒): *
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5410/AD5420
Data Sheet
Rev. F | Page 12 of 32
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
–40
–20
0
20
40
60
80
T
O
T
AL
UNADJUS
T
E
D
E
RRO
R
(
%F
S
R)
TEMPERATURE (°C)
AVDD = 24V
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
07027-
013
Figure 13. Total Unadjusted Error vs. Temperature
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
–40
–20
0
20
40
60
80
OFFS
E
T
E
R
OR
(
%
FS
R
)
TEMPERATURE (°C)
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
AVDD = 24V
07027-
017
Figure 14. Offset Error vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
–40
–20
0
20
40
60
80
G
AI
N
E
RRO
R
(
%
F
S
R)
TEMPERATURE (°C)
AVDD = 24V
07027-
018
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
Figure 15. Gain Error vs. Temperature
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
10
15
20
25
30
35
40
07027-
011
INL
E
RRO
R
(
%
F
S
R)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
Figure 16. Integral Nonlinearity Error vs. AVDD, External RSET
–0.015
–0.020
–0.010
–0.005
0.005
0.015
0
0.010
0.020
10
15
20
25
30
35
40
07027-
014
INL
E
RRO
R
(
%F
S
R)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
Figure 17. Integral Nonlinearity Error vs. AVDD, Internal RSET
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
10
15
20
25
30
35
40
DN
L
E
RRO
R
(L
S
B
)
AVDD (V)
07027-
012
TA = 25°C
0mA TO 24mA RANGE
Figure 18. Differential Nonlinearity Error vs. AVDD, External RSET
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