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參數(shù)資料
| 型號： | AD5532HSABCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH HS 74-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 1.1M |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
REV. 0
AD5532HS
–8–
FUNCTIONAL DESCRIPTION
The AD5532HS consists of 32 DACs in a single package. A
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (VOUT0–VOUT31).
To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the 5-bit DAC address
and 14-bit DAC data have been loaded the selected DAC
converts the code.
On power-on, all the DACs are loaded with zeros.
Digital-to-Analog Section
The architecture of each DAC channel consists of a resistor-
string DAC followed by an output buffer amplifier. The voltage
at the REF_IN pin provides the reference voltage for the cor-
responding DAC. Since the input coding to the DAC is straight
binary, the ideal DAC output voltage is given by:
V
VD
DAC
REF
IN
=
×
_
2
14
where D = decimal equivalent of the binary code that is loaded
to the DAC register i.e., 0–16,383.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the
0 V–2.5 V output of the DAC to a wider range. This is done by
gaining up the DAC output by two and offsetting the voltage
by the voltage on OFFS_IN pin.
VV
V
OUT
DAC
OFFS
IN
=×
() –
_
2
VDAC is the output of the DAC.
VOFFS_IN is the voltage at the OFFS_IN pin.
Table I shows how the output range of VOUT relates to the offset
voltage supplied by the user.
Table I. Sample Output Voltage Ranges
VOFFS_IN
VDAC
VOUT
(V)
0
0 to 2.5
0 to 5
2.5
0 to 2.5
–2.5 to +2.5
VOUT is limited only by the headroom of the output amplifiers.
VOUT must be within maximum ratings.
Reset Function
The reset function on the AD5532HS can be used to reset all
nodes on the device to their power-on-reset condition. All the
DACs are loaded with 0s and all registers are cleared. The reset
function is implemented by taking the RESET pin low.
SERIAL INTERFACE
The serial interface is controlled by three pins as follows:
SYNC: This pin is the Frame Synchronization pin for the serial
interface.
SCLK: This pin is the Serial Clock Input. It operates at clock
speeds up to 30 MHz.
DIN: This pin is the Serial Data Input. Data must be valid on
the falling edge of SCLK.
To update a single DAC channel a 19-bit data-word is written
into the AD5532HS. See Table II.
Table II. Serial Data Format
MSB
LSB
A4
A3
A2
A1
A0
DB13–DB0
A4–A0 Bits
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
DB13–DB0 Bits
These are used to write a 14-bit word into the addressed
DAC register.
Figure 1 shows the timing diagram for a serial write to the
AD5532HS. The serial interface works with both a continuous and
a noncontinuous serial clock. The first falling edge of SYNC resets
a counter that counts the number of serial clocks to ensure
the correct number of bits are shifted in and out of the serial
shift registers. Any further edges on SYNC are ignored until the
correct number of bits are shifted in or out. Once 19 bits have
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place, the counter must be reset by the
falling edge of SYNC. The user must allow 280 ns (min)
between successive writes (refer to Timing Specifications).
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| AD5533 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Infinite Sample-and-Hold |
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