- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8553 > AD5532HSABCZ (Analog Devices Inc)IC DAC 14BIT 32CH HS 74-CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD5532HSABCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 32CH HS 74-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 1.1M |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
REV. 0
AD5532HS
–9–
MICROPROCESSOR INTERFACING
AD5532HS-to-ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5532HS without the need for extra logic.
A data transfer is initiated by writing a word to the Tx register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532HS on the falling edge of its SCLK.
The easiest way to provide the 19-bit data-word required by
the AD5532HS, is to transmit two 10-bit data-words from the
ADSP-21xx. Ensure that the data is positioned correctly in the
TX register so that the first 19 bits transmitted contain valid
data. The SPORT control register should be set up as follows:
TFSW
= 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK
= 1, Internal Serial Clock
TFSR
= 1, Frame Every Word
ITFS
= 1, Internal Framing Signal
SLEN
= 1001, 10-Bit Data Word
Figure 3 shows the connection diagram.
SCLK
AD5532HS*
SYNC
TFS
DIN
DT
SCLK
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface
AD5532HS-to-MC68HC11 Interface
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5532HS and the MOSI output drives the serial data line
(DIN) of the AD5532HS. The SYNC signal is derived from a port
line (PC7). When data is being transmitted to the AD5532HS, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. The 68HC11 transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive write operations are necessary to
transmit 19 bits of data. Data is transmitted MSB first. It is
important to left-justify the data in the SPDR register so that
the first 19 bits transmitted contain valid data. PC7 must be
pulled low to start a transfer. It is taken high and pulled low
again before any further write cycles can take place. See Figure 4.
SCLK
AD5532HS*
SYNC
DIN
PC7
SCK
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY
MOSI
Figure 4. AD5532HS-to-MC68HC11 Interface
AD5532HS-to-PIC16C6x/7x Interface
The PIC16C6x/7x Synchronous Serial Port (SSP) is configured
as an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
In this example I/O port RA1 is being used to pulse SYNC
and enable the serial port of the AD5532HS. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left-justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1
must be pulled low to start a transfer. It is taken high and pulled
low again before any further write cycles can take place. Figure 5
shows the connection diagram.
SCLK
PIC16C6x/7x*
SYNC
DIN
SCK/RC3
AD5532HS*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDI/RC4
RA1
Figure 5. AD5532HS-to-PIC16C6x/7x Interface
AD5532HS-to-8051 Interface
The AD5532HS requires a clock synchronized to the serial
data. The 8051 serial interface must therefore be operated in
Mode 0. In this mode serial data exits the 8051 through RxD
and a shift clock is output on TxD. The SYNC signal is derived
from a port line (P1.1). Figure 6 shows how the 8051 is connected
to the AD5532HS. Because the AD5532HS shifts data out on
the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. Note also that
the AD5532HS requires its data with the MSB first. Since the
8051 outputs the LSB first, the transmit routine must take this
into account.
AD5532HS*
SCLK
DIN
SYNC
TxD
RxD
P1.1
8051*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD5532HS-to-8051 Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5532ABCZ-5 | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| VI-B4L-MU-S | CONVERTER MOD DC/DC 28V 200W |
| VE-JT1-MW-S | CONVERTER MOD DC/DC 12V 100W |
| AD5532ABCZ-2 | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| VE-J53-MW-S | CONVERTER MOD DC/DC 24V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5533 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Infinite Sample-and-Hold |
| AD5533ABC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
| AD5533ABC-1REEL | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA T/R |
| AD5533ABCZ-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
| AD5533B | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Precision Infinite Sample-and-Hold |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。