參數(shù)資料
型號(hào)： AD5744RCSUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/32頁(yè)
文件大小： 0K
描述： IC DAC 4CH 14BIT SER 1LSB 32TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5764(R), AD5744R Product Change 04/Sept/2009
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 10µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 387mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 管件
輸出數(shù)目和類型： 4 電壓，雙極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 784 (CN2011-ZH PDF)
Data Sheet
AD5744R
Rev. E | Page 11 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D1
D0
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
RS
T
O
UT
RS
T
IN
DG
ND
DV
CC
AV
DD
PG
N
D
IS
C
AV
SS
BI
N/
2s
C
O
M
P
AV
DD
AV
SS
TE
M
P
RE
F
G
ND
RE
F
O
UT
RE
F
CD
RE
F
AB
1
2
3
4
5
6
7
8
23
22
21
18
19
20
24
17
PIN 1
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
AD5744R
TOP VIEW
(Not to Scale)
0
606
5-
0
06
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred
in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds of up to 30 MHz.
3
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
4
SDO
Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode.
5
CLR
Negative Edge Triggered Input.1 Asserting this pin sets the data register to 0x0000.
6
LDAC
Load DAC. This logic input is used to update the data register and, consequently, the analog outputs. When tied
permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held high during
the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of
LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC
pin must not be left unconnected.
7, 8
D0, D1
Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak internal
pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
9
RSTOUT
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it
can be used to control other system components.
10
RSTIN
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps
the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged.
11
DGND
Digital Ground Pin.
12
DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
13, 31
AVDD
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
14
PGND
Ground Reference Point for Analog Circuitry.
15, 30
AVSS
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
16
ISCC
This pin is used in association with an optional external resistor to AGND to program the short-circuit current of
the output amplifiers. Refer to the Design Features section for more information.
17
AGNDD
Ground Reference Pin for DAC D Output Amplifier.
18
VOUTD
Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
19
VOUTC
Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
20
AGNDC
Ground Reference Pin for DAC C Output Amplifier.
21
AGNDB
Ground Reference Pin for DAC B Output Amplifier.
22
VOUTB
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
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