參數(shù)資料
型號(hào)： AD5750BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 0K
描述： IC CURR/VOLT OUT DVR 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
放大器類型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 2 V/µs
電流 - 電源： 5.2mA
電流 - 輸出 / 通道： 24mA
電壓 - 電源，單路/雙路(±)： ±10.8 V ~ 26.4 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
AD5750/AD5750-1
Rev. C | Page 29 of 36
DETAILED DESCRIPTION OF FEATURES
OUTPUT FAULT ALERT—SOFTWARE MODE
In software mode, the AD5750/AD5750-1 are equipped with
one FAULT pin; this is an open-drain output allowing several
AD5750/AD5750-1 devices to be connected together to one
pull-up resistor for global fault detection. In software mode, the
FAULT pin is forced active low by any one of the following fault
scenarios:
The voltage at IOUT attempts to rise above the compliance
range due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with window limits
because this requires an actual output error before the fault
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approximately 1 V of remaining drive capability.
Thus, the fault output activates slightly before the com-
pliance limit is reached. Because the comparison is made
within the feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain, and an
output error does not occur before the fault output
becomes active.
A short is detected on the voltage output pin (VOUT). The
short-circuit current is limited to 15 mA.
An interface error is detected due to packet error checking
(PEC) failure. See the Packet Error Checking section.
If the core temperature of the AD5750/AD5750-1 exceeds
approximately 150°C.
OUTPUT FAULT ALERT—HARDWARE MODE
In hardware mode, the AD5750/AD5750-1 are equipped with
three fault pins: VFAULT, IFAULT, and TEMP. These are open-
drain outputs allowing several AD5750/AD5750-1 devices to
be connected together to one pull-up resistor for global fault
detection. In hardware control mode, these fault pins are forced
active by any one of the following fault scenarios:
An open circuit is detected. The voltage at IOUT attempts
to rise above the compliance range, due to an open-loop
circuit or insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with window limits because this requires an
actual output error before the fault output becomes active.
Instead, the signal is generated when the internal amplifier
in the output stage has less than approximately 1 V of
remaining drive capability. Thus, the fault output activates
slightly before the compliance limit is reached. Because the
comparison is made within the feedback loop of the output
amplifier, the output accuracy is maintained by its open-
loop gain, and an output error does not occur before the
fault output becomes active. If this fault is detected, the
IFAULT pin is forced low.
A short is detected on the voltage output pin (VOUT). The
short-circuit current is limited to 15 mA. If this fault is
detected, the VFAULT pin is forced low.
The core temperature of the AD5750/AD5750-1 exceeds
approximately 150°C. If this fault is detected, the TEMP
pin is forced low.
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION
Under normal operation, the voltage output sinks and sources
up to 12 mA and maintains specified operation. The maximum
current that the voltage output delivers is 15 mA; this is the
short-circuit current.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that allows the voltage output
to be cleared to either zero-scale code or midscale code, and is
user-selectable via the CLRSEL pin or the CLRSEL bit of the input
shift register, as described in Table 8. (The clear select feature is
a logical OR function of the CLRSEL pin and the CLRSEL bit).
The current loop output clears to the bottom of its programmed
range. When the CLEAR signal is returned low, the output returns
to its programmed value or to a new programmed value. A clear
operation can also be performed via the clear command in the
control register.
Table 11. CLRSEL Options
CLRSEL
Output Clear Value
Unipolar Output
Voltage Range
Unipolar Current Output Range
Bipolar Output Range
Bipolar Current
Output Range
0
0 V
Zero scale; for example,
4 mA on the 4 mA to 20 mA range
0 mA on the 0 mA to 20 mA range
Negative full scale
Zero scale; for example,
24 mA on the ±24 mA range
1
Midscale
Midscale; for example,
12 mA on the 4 mA to 20 mA range
10 mA on the 0 mA to 20 mA range
0 V
Midscale; for example,
0 mA on the ±24 mA range
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