Referring to Figure 1, RSET
參數(shù)資料
型號(hào)： AD5750BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 24/36頁
文件大?。?/td> 0K
描述： IC CURR/VOLT OUT DVR 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
放大器類型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 2 V/µs
電流 - 電源： 5.2mA
電流 - 輸出 / 通道： 24mA
電壓 - 電源，單路/雙路(±)： ±10.8 V ~ 26.4 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
AD5750/AD5750-1
Rev. C | Page 30 of 36
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor and is
part of the voltage-to-current conversion circuitry. The nominal
value of the internal current sense resistor is 15 kΩ. To allow for
overrange capability in current mode, the user can also select
the internal current sense resistor to be 14.7 kΩ, giving a
nominal 2% overrange capability. This feature is available in the
0 mA to 20 mA, 4 mA to 20 mA, and ±20 mA current ranges.
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature,
an external low drift resistor can be connected to the REXT1
and REXT2 pins of the AD5750/AD5750-1, which can be used
instead of the internal resistor. The external resistor is selected
via the input shift register. If the external resistor option is not
used, the REXT1 and REXT2 pins should be left floating.
PROGRAMMABLE OVERRANGE MODES
The AD5750/AD5750-1 contain an overrange mode for most of
the available ranges. The overranges are selected by configuring
the R3, R1, R1, and R0 bits (or pins) accordingly.
In voltage mode, the overranges are typically 20%, providing
programmable output ranges of 0 V to 6 V, 0 V to 12 V, ±6 V,
and ±12 V. The analog input remains the same.
In current mode, the overranges are typically 2%. In current
mode, the overrange capability is only available on three ranges,
0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these
ranges, the analog input also remains the same (0 V to 4.096 V
for the AD5750, 0 V to 2.5 V for the AD5750-1).
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5750/AD5750-1 offer the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5750/AD5750-1 should generate an 8-bit
frame check sequence using the following polynomial:
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5750/AD5750-1 before taking SYNC high. If the
AD5750/AD5750-1 receive a 24-bit data frame, the parts
perform the error check when SYNC goes high. If the check is
valid, then the data is written to the selected register. If the error
check fails, the FAULT pin goes low and Bit D3 of the status
register is set. After reading this register, this error flag is
cleared automatically and the FAULT pin goes high again.
SCLK
SDIN
SYNC
UPDATE ON SYNC HIGH
D15
(MSB)
D0
(LSB)
16-BIT DATA
16-BIT DATA TRANSER—NO ERROR CHECKING
SCLK
SDIN
SYNC
FAULT
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
FAULT GOES LOW IF
ERROR CHECK FAILS
D23
(MSB)
D8
(LSB)
D7
D0
16-BIT DATA
8-BIT FCS
16-BIT DATA TRANSER WITH ERROR CHECKING
072
68-
049
Figure 55. PEC Error Checking Timing
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