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參數(shù)資料
| 型號(hào)： | AD5755-1ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SERIAL 64LFCSP |
| 視頻文件： | AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 設(shè)置時(shí)間： | 11µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，4 電壓 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5755-1
Rev. E | Page 37 of 52
Software Register
The software register has three functions. It allows the user to
perform a software reset to the part. It can be used to set the
user toggle bit, D11, in the status register. It is also used as part
of the watchdog feature when it is enabled. This feature is useful
to ensure that communication has not been lost between the
MCU and the AD5755-1 and that the datapath lines are working
properly (that is, SDIN, SCLK, and SYNC).
When the watchdog feature is enabled, the user must write
0x195 to the software register within the timeout period. If this
command is not received within the timeout period, the ALERT
pin signals a fault condition. This is only required when the
watchdog timer function is enabled.
DC-to-DC Control Register
The dc-to-dc control register allows the user control over
the dc-to-dc switching frequency and phase, as well as the
maximum allowable dc-to-dc output voltage. The dc-to-dc
control register options are shown in Table 24 and Table 25.
Table 22. Programming the Software Register
MSB
LSB
D15
D14
D13
D12
D11 to D0
1
0
User program
Reset code/SPI code
Table 23. Software Register Functions
Bit
Description
User Program
This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is
set to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be
used to ensure that the SPI pins are working correctly by writing a known bit value to this register and
reading back the corresponding bit from the status register.
Reset Code/SPI Code
Option
Description
Reset code
Writing 0x555 to D[11:0] performs a reset of the AD5755-1.
SPI code
If the watchdog timer feature is enabled, 0x195 must be written to the software register
(D11 to D0) within the programmed timeout period.
Table 24. Programming the DC-to-DC Control Register
MSB
LSB
D15
D14
D13
D12 to D7
D6
D5 to D4
D3 to D2
D1 to D0
0
1
DC-DC Comp
DC-DC phase
DC-DC Freq
DC-DC MaxV
1 X = don’t care.
Table 25. DC-to-DC Control Register Options
Bit
Description
DC-DC Comp
Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter
CC Supply Requirements—Slewing sections in the Device Features section for more
information.
0 = selects the internal 150 k compensation resistor (default).
1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc
compensation resistor must be used; this is placed at the COMP
DCDC_x pin in series with the 10 nF dc-to-dc compensation
capacitor to ground. Typically, a ~50 k resistor is recommended.
DC-DC Phase
User programmable dc-to-dc converter phase (between channels).
00 = all dc-to-dc converters clock on the same edge (default).
01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges.
10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges.
11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.
DC-DC Freq
DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 69 and Figure 70).
00 = 250 ± 10% kHz.
01 = 410 ± 10% kHz (default).
10 = 650 ± 10% kHz.
DC-DC MaxV
Maximum allowed V
BOOST_x voltage supplied by the dc-to-dc converter.
00 = 23 V + 1 V/1.5 V (default).
01 = 24.5 V ± 1 V.
10 = 27 V ± 1 V.
11 = 29.5 V ± 1V.
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