參數(shù)資料
型號(hào)： AD5755BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/52頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD 64-LFCSP
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
標(biāo)準(zhǔn)包裝： 750
設(shè)置時(shí)間： 11µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，4 電壓
采樣率（每秒）： *
AD5755
Data Sheet
Rev. C | Page 30 of 52
Even though the output ranges are not enabled, the default
output range is 0 V to 5 V, and the clear code register is loaded
with all zeros. This means that if the user clears the part after
power-up, the output is actively driven to 0 V (if the channel
has been enabled for clear).
After device power on, or a device reset, it is recommended to
wait 100 μs or more before writing to the device to allow time
for internal calibrations to take place.
SERIAL INTERFACE
The AD5755 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking, or PEC (see the Device Features
section), is enabled, an additional eight bits must be written to
the AD5755, creating a 32-bit serial interface.
There are two ways in which the DAC outputs can be updated:
individual updating or simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the DAC data register. The addressed DAC output is updated on
the rising edge of SYNC. See Table 3 and Figure 3 for timing
information.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the DAC data register. Only the first write to each channel’s
DAC data register is valid after LDAC is brought high. Any subse-
quent writes while LDAC is still held high are ignored, though
they are loaded into the DAC data register. All the DAC outputs
are updated by taking LDAC low after SYNC is taken high.
VOUT_x
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
VREFIN
SYNC
DAC DATA
REGISTER
OFFSET
AND GAIN
CALIBRATION
DAC INPUT
REGISTER
SCLK
07304-
072
Figure 73. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
TRANSFER FUNCTION
Table 6 shows the input code to ideal output voltage relationship
for the AD5755 for straight binary data coding of the ±10 V
output range.
Table 6. Ideal Output Voltage to Input Code Relationship
Digital Input
Straight Binary Data Coding
Analog Output
MSB
LSB
VOUT
1111
+2 VREF × (32,767/32,768)
1111
1110
+2 VREF × (32,766/32,768)
1000
0000
0 V
0000
0001
2 VREF × (32,767/32,768)
0000
2 VREF
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