參數資料
| 型號： | AD5755BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 37/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QUAD 64-LFCSP |
| 視頻文件： | AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC |
| 標準包裝： | 750 |
| 設置時間： | 11µs |
| 位數： | 16 |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 4 |
| 電壓電源： | 模擬和數字，雙 ± |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 4 電流，4 電壓 |
| 采樣率（每秒）： | * |
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AD5755
Data Sheet
Rev. C | Page 42 of 52
directly to the gain/TUE error of the AD5755 with the external
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5755 allows the user to
control the rate at which the output value changes. This feature
is available on both the current and voltage outputs. With the
slew rate control feature disabled, the output value changes at a
rate limited by the output drive circuitry and the attached load.
To reduce the slew rate, this can be achieved by enabling the
slew rate control feature. With the feature enabled via the SREN
bit of the slew rate control register (see Table 26), the output,
instead of slewing directly between two values, steps digitally
at a rate defined by two parameters accessible via the slew rate
control register, as shown in Table 26. The parameters are
SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at
which the digital slew is updated, for example, if the selected
update rate is 8 kHz, the output updates every 125 s. In conjunc-
tion with this, SR_STEP defines by how much the output value
changes at each update. Together, both parameters define the
rate of change of the output value. Table 31 and Table 32 outline
the range of values for both the SR_CLOCK and SR_STEP
parameters.
Table 31. Slew Rate Update Clock Options
SR_CLOCK
Update Clock Frequency (Hz)1
0000
64 k
0001
32 k
0010
16 k
0011
8 k
0100
4 k
0101
2 k
0110
1 k
0111
500
1000
250
1001
125
1010
64
1011
32
1100
16
1101
8
1110
4
1111
0.5
1
These clock frequencies are divided down from the 13 MHz internal
Table 32. Slew Rate Step Size Options
SR_STEP
Step Size (LSBs)
000
1
001
2
010
4
011
16
100
32
101
64
110
128
111
256
The following equation describes the slew rate as a function of
the step size, the update clock frequency, and the LSB size:
Size
LSB
Frequency
Clock
Update
Size
Step
Change
Output
Time
Slew
×
=
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for IOUT_x or volts for VOUT_x.
When the slew rate control feature is enabled, all output
changes occur at the programmed slew rate (see the DC-to-DC
Converter Settling Time section for additional information).
For example, if the CLEAR pin is asserted, the output slews to
the clear value at the programmed slew rate (assuming that the
clear channel is enabled to be cleared). If a number of channels
are enabled for slew, care must be taken when asserting the clear
pin. If one of the channels is slewing when clear is asserted,
other channels may change directly to their clear values not
under slew rate control. The update clock frequency for any
given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
POWER DISSIPATION CONTROL
The AD5755 contains integrated dynamic power control using
a dc-to-dc boost converter circuit, allowing reductions in power
consumption from standard designs when using the part in
current output mode.
In standard current input module designs, the load resistor
values can range from typically 50 to 750 . Output module
systems must source enough voltage to meet the compliance
voltage requirement across the full range of load resistor values.
For example, in a 4 mA to 20 mA loop when driving 20 mA, a
compliance voltage of >15 V is required. When driving 20 mA
into a 50 load, only 1 V compliance is required.
The AD5755 circuitry senses the output voltage and regulates
this voltage to meet compliance requirements plus a small
headroom voltage. The AD5755 is capable of driving up to
24 mA through a 1 k load.
DC-TO-DC CONVERTERS
The AD5755 contains four independent dc-to-dc converters.
These are used to provide dynamic control of the VBOOST supply
voltage for each channel (see Figure 72). Figure 78 shows the
discrete components needed for the dc-to-dc circuitry, and the
following sections describe component selection and operation
of this circuitry.
AVCC
LDCDC
DDCDC
CDCDC
4.7F
CFILTER
0.1F
RFILTER
CIN
SWx
VBOOST_x
≥10F
10
10H
07304-
077
Figure 78. DC-to-DC Circuit
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD5755BCPZX | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control |
| AD5757 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control |
| AD5757_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control |
| AD5757ACPZ | 功能描述:IC DAC 16BIT QUAD 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數:12 數據接口:串行，SPI? 轉換器數目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5757ACPZ-REEL7 | 功能描述:IC DAC 16BIT QUAD IOUT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數:16 數據接口:并聯 轉換器數目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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