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參數(shù)資料
| 型號： | AD5765BSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 5V QUAD 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 設(shè)計(jì)資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073) |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 76mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | * |
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AD5765
Data Sheet
Rev. C | Page 20 of 28
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
No operation, data = don’t care
0
1
Don’t care
Local ground
offset adjustment
D1
direction
D1
value
D0
direction
D0
value
SDO
disable
0
1
0
Clear, data = don’t care
0
1
0
1
Load, data = don’t care
Table 12. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local Ground
Offset Adjustment
Set by the user to enable the local ground offset adjustment function. Cleared by the user to disable the local ground
offset adjustment function (default). See the Design Features section for additional details.
D0/D1 Direction
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). See the Design
Features section for additional details.
D0/D1 Value
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input.
When enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Clear
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Load
Addressing this function updates the DAC registers and, consequently, the analog outputs.
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The data bits are in the DB15 to DB0 positions, as shown in Table 13.
Table 13. Programming the AD5765 Data Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB0
0
1
0
DAC address
16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each
DAC, as shown in Table 14 and Table 15.
Table 14. Programming the AD5765 Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB2
DB1
DB0
0
1
DAC address
Don’t care
CG1
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
±4.096 V (default)
0
±4.20103 V
0
1
±4.31158 V
1
0
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