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參數(shù)資料
| 型號： | AD5765BSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 5V QUAD 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 設(shè)計資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073) |
| 標準包裝： | 500 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 76mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5765
Rev. C | Page 17 of 28
THEORY OF OPERATION
The AD5765 is a quad, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of ±4.75 V to ±5.25 V and
has a buffered output voltage of up to ±4.311 V. Data is written to
the AD5765 in a 24-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy-
chaining or readback.
The AD5765 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with 0x0000.
The AD5765 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain, and offset registers.
DAC ARCHITECTURE
The DAC architecture of the AD5765 consists of a 16-bit
current mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 25.
The four MSBs of the 16-bit data-word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of the
15 matched resistors to either AGNDx or IOUT. The remaining
12 bits of the data-word drive switches S0 to S11 of the 12-bit
R-2R ladder network.
2R
E15
VREF
2R
E14
E1
2R
S11
R
2R
S10
2R
12-BIT, R-2R LADDER
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
VOUTx
2R
S0
2R
AGNDx
R/8
IOUT
07249-
060
Figure 25. DAC Ladder Structure
REFERENCE BUFFERS
The AD5765 operates with an external reference. The reference
inputs (REFAB and REFCD) have an input range up to 2.1 V.
This input voltage is then used to provide a buffered positive
and negative reference for the DAC cores. The positive
reference is given by
+VREF = 2 VREF
The negative reference to the DAC cores is given by
VREF = 2 VREF
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
SERIAL INTERFACE
The AD5765 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits as shown in Table 9. The timing diagram for this operation
is shown in Figure 2.
At power-up, the DAC registers are loaded with zero code
(0x0000), and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at
this time by asserting either LDAC or CLR. The corresponding
output voltage depends on the state of the BIN/2sCOMP pin.
If the BIN/2sCOMP pin is tied to DGND, the data coding is
twos complement, and the outputs update to 0 V. If the
BIN/2sCOMP pin is tied to DVCC, the data coding is offset
binary, and the outputs update to negative full scale. To have the
outputs power up with zero code loaded to the outputs, the CLR
pin should be held low during power-up.
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the data
written is invalid. If more than 24 falling SCLK edges are applied
before SYNC is brought high, the input data is also invalid. The
input register addressed is updated on the rising edge of SYNC.
In order for another serial transfer to take place, SYNC must be
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low.
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