參數(shù)資料
型號(hào): AD5765BSUZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/28頁(yè)
文件大小: 0K
描述: IC DAC 16BIT 5V QUAD 32-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5763/65 Metal Layer Edit Change 08/Sept/2009
設(shè)計(jì)資源: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073)
標(biāo)準(zhǔn)包裝: 500
設(shè)置時(shí)間: 8µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 76mW
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 4 電壓,雙極
采樣率(每秒): *
Data Sheet
AD5765
Rev. C | Page 21 of 28
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by 32 LSBs to +31 LSBs in 1 LSB increments as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale
and negative full-scale points simultaneously, each point being adjusted by of one step. The fine gain register coding is twos complement.
Table 16. Programming AD5765 Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
DAC address
Don’t care
FG5
FG4
FG3
FG2
FG1
FG0
Table 17. AD5765 Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+31 LSBs
0
1
+30 LSBs
0
1
0
...
No Adjustment (Default)
0
31 LSBs
1
0
1
32 LSBs
1
0
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The AD5765 offset register is an 8-bit register and allows the user to adjust the offset of each channel
by 16 LSBs to +15.875 LSBs in increments of LSB as shown in Table 18 and Table 19. The offset register coding is twos complement.
Table 18. Programming the AD5765 Offset Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
DAC address
Don’t care
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
Table 19. AD5765 Offset Register Options
Offset Adjustment
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
+15.875 LSBs
0
1
+15.75 LSBs
0
1
0
No Adjustment (Default)
0
15.875 LSBs
1
0
1
16 LSBs
1
0
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