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參數(shù)資料
| 型號： | AD5765BSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 5V QUAD 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 設(shè)計資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073) |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 76mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | * |
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AD5765
Data Sheet
Rev. C | Page 22 of 28
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPLE
Using the information provided in the Theory of Operation
section, the following worked example demonstrates how the
AD5765 functions can be used to eliminate both offset and gain
errors. Because the AD5765 is factory calibrated, offset and gain
errors should be negligible. However, errors can be introduced
by the system that the AD5765 is operating within; for example,
a voltage reference value that is not equal to 2.048 V introduces
a gain error. An output range of ±4.096 V and twos complement
data coding are assumed.
Removing Offset Error
The AD5765 can eliminate an offset error in the range of 2 mV to
+1.98 mV with a step size of of a 16-bit LSB.
1. Calculate the step size of the offset adjustment.
μV
625
.
15
8
2
192
.
8
16
=
×
=
Size
Step
Adjust
Offset
2. Measure the offset error by programming 0x0000 to the
data register and measuring the resulting output voltage;
for this example, the measured value is 614 V.
3. Calculate the number of offset adjustment steps that this
value represents.
Steps
13
μV
625
.
15
μV
614
=
Size
Step
Offset
Value
Offset
Measured
Steps
of
Number
The offset error measured is positive; therefore, a negative
adjustment of 40 steps is required. The offset register is 8-bits
wide and the coding is twos complement.
The required offset register value can be calculated as follows:
1. Convert the adjustment value to binary: 00101000.
2. Convert the binary number to a negative twos complement
number by inverting all bits and adding 1: 11011000.
11011000 is the value that should be programmed to the
offset register.
Note that this twos complement conversion is not
necessary in the case of a positive offset adjustment. The
value to be programmed to the offset register is simply the
binary representation of the adjustment value.
Removing Gain Error
The AD5765 can eliminate a gain error at negative full-scale
output in the range of 2 mV to +1.94 mV with a step size of
of a 16-bit LSB.
1. Calculate the step size of the gain adjustment.
μV
5
.
62
2
192
.
8
16
=
×
=
Size
Step
Adjust
Gain
2. Measure the gain error by programming 0x8000 to the data
register and measuring the resulting output voltage. The
gain error is the difference between this value and 4.096 V;
for this example, the gain error is 0.8 mV.
3. Calculate how many gain adjustment steps this value
represents.
Steps
13
μV
5
.
62
mV
8
.
0
=
Size
Step
Gain
Value
Gain
Measured
Steps
of
Number
The gain error measured is negative (in terms of magnitude);
therefore, a positive adjustment of 13 steps is required. The gain
register is six bits wide and the coding is twos complement.
The required gain register value can be determined as follows:
1. Convert the adjustment value to binary: 001101.
The value to be programmed to the gain register is simply
this binary number.
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