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參數(shù)資料
| 型號： | AD6653-125EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機 |
| 文件頁數(shù)： | 43/80頁 |
| 文件大?。?/td> | 1998K |
| 代理商： | AD6653-125EBZ |
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AD6653
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Rev. 0 | Page 43 of 80
Table 23. Mode Selection
Pin
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND
(default)
AVDD
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
Chip in power-down or
standby
Normal operation
SMI SCLK/PDWN
AGND
(default)
SPI ACCESSIBLE FEATURES
Table 24 provides a brief description of the general features
that
are accessible via the SPI. These features are described in
Application Note AN-877,
Interfacing to High Speed ADCs via
SPI
(see www.analog.com). The AD6653 part-specific features
are described in the Memory Map Register Description section.
Table 24. Features Accessible Using the SPI
Feature Name
Description
Modes
Allows the user to set either power-down
mode or standby mode
Clock
Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have
known data on output bits
Output Mode
Allows the user to set up outputs
Output Phase
Allows the user to set the output clock polarity
Output Delay
Allows the user to vary the DCO delay
VREF
Allows the user to set the reference voltage.
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
CLK
t
DS
t
H
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
t
LOW
t
HIGH
0
Figure 79. Serial Port Interface Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6653BCPZ-125 | IF Diversity Receiver |
| AD6653BCPZ-150 | IF Diversity Receiver |
| AD6655BCPZ-1251 | IF Diversity Receiver |
| AD6655 | IF Diversity Receiver |
| AD6655-125EBZ1 | IF Diversity Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653-150EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk |
| AD6653BCPZ-125 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
| AD6654 | 制造商:Analog Devices 功能描述:- Bulk |
| AD6654/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver |
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