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| 型號： | AD6653 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機(jī) |
| 文件頁數(shù)： | 36/80頁 |
| 文件大?。?/td> | 1998K |
| 代理商： | AD6653 |
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AD6653
When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock
cycles, and the greater of the two input samples is output at the
DCO rate. Table 19 shows the corresponding ADC input levels
when the fast detect mode select bits are set to 0b001 (that is,
when the ADC fast magnitude is presented on the FD[3:1] pins).
Rev. 0 | Page 36 of 80
Table 19. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 001
ADC Fast
Magitude on
FD[2:0] Pins
Below FS (dB)
000
<24
001
24 to 14.5
010
14.5 to 10
011
10 to 7
100
7 to 5
101
5 to 3.25
110
3.25 to 1.8
111
1.8 to 0
Nominal Input
Magnitude
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to 18.07
30.14 to 12.04
18.07 to 8.52
12.04 to 6.02
8.52 to 4.08
6.02 to 2.5
4.08 to 1.16
2.5 to 0
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD[2:1]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 20.
Table 20. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 010 or 011
ADC Fast
Magitude on
FD[2:1] Pins
Below FS (dB)
00
<14.5
01
14.5 to 7
10
7 to 3.25
11
3.25 to 0
Nominal Input
Magnitude
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to 12.04
18.07 to 6.02
8.52 to 2.5
4.08 to 0
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 12 ADC clock cycles. An overrange at the
input is indicated by this bit 12 clock cycles after it occurs.
GAIN SWITCHING
The AD6653 includes circuitry that is useful in applications either
where large dynamic ranges exist or where gain ranging converters
are employed. This circuitry allows digital thresholds to be set
such that an upper threshold and a lower threshold can be
programmed. Fast detect mode select bits = 010 through fast
detect mode select bits = 101 support various combinations of
the gain switching options.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in
the coarse upper threshold register (Address 0x105[2:0]). This
value is compared with the ADC Fast Magnitude Bits[2:0]. The
coarse upper threshold output is output two clock cycles after
the level is exceeded at the input and, therefore, provides a fast
indication of the input signal level. The coarse upper threshold
levels are shown in Table 21. This indicator remains asserted for a
minimum of two ADC clock cycles or until the signal drops
below the threshold level.
Table 21. Coarse Upper Threshold Levels
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
000
<24
001
24
010
14.5
011
10
100
7
101
5
110
3.25
111
1.8
Coarse Upper Threshold
Register[2:0]
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input
magnitude exceeds the value programmed in the fine upper
threshold register located in Register 0x106 and Register 0x107.
The 13-bit threshold register is compared with the signal
magnitude at the output of the ADC. This comparison is subject
to the ADC clock latency but is accurate in terms of converter
resolution. The fine upper threshold magnitude is defined by
the following equation:
dBFS
= 20 log(
Threshold Magnitude
/2
13
)
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input
magnitude is less than the value programmed in the fine lower
threshold register located at Register 0x108 and Register 0x109.
The fine lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to ADC clock latency but is accurate
in terms of converter resolution. The fine lower threshold
magnitude is defined by the following equation:
dBFS
= 20 log(
Threshold Magnitude
/2
13
)
The operation of the fine upper threshold and fine lower
threshold indicators is shown in Figure 73.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6653-125EBZ | IF Diversity Receiver |
| AD6653BCPZ-125 | IF Diversity Receiver |
| AD6653BCPZ-150 | IF Diversity Receiver |
| AD6655BCPZ-1251 | IF Diversity Receiver |
| AD6655 | IF Diversity Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653-125EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653 |
| AD6653-150EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk |
| AD6653BCPZ-125 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
| AD6654 | 制造商:Analog Devices 功能描述:- Bulk |
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