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參數(shù)資料
| 型號： | AD6653 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機 |
| 文件頁數(shù)： | 37/80頁 |
| 文件大?。?/td> | 1998K |
| 代理商： | AD6653 |
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AD6653
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in
conjunction with the coarse upper threshold bits, asserting
when the input magnitude is greater than the 3-bit value in the
coarse upper threshold register (Address 0x105). The increment
gain indicator, similarly, corresponds to the fine lower threshold
bits except that it is asserted only if the input magnitude is less
than the value programmed in the fine lower threshold register
after the dwell time elapses. The dwell time is set by the 16-bit
dwell time value located at Address 0x10A and Address 0x10B
and is set in units of ADC input clock cycles ranging from 1 to
65,535. The fine lower threshold register is a 13-bit register that
Rev. 0 | Page 37 of 80
is compared with the magnitude at the output of the ADC. This
comparison is subject to the ADC clock latency but allows a
finer, more accurate comparison. The fine upper threshold
magnitude is defined by the following equation:
dBFS
= 20 log(
Threshold Magnitude
/2
13
)
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and decrement gain
output is shown graphically in Figure 73.
UPPER THRESHOLD (COARSE OR FINE)
FINE LOWER THRESHOLD
IG
DG
F_LT
C_UT OR F_UT*
DWELL TIME
TIMER RESET BY
RISE ABOVE F_LT
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
Figure 73. Threshold Settings for C_UT, F_UT, F_LT, DG, and IG
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
DWELL TIME
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6653-125EBZ | IF Diversity Receiver |
| AD6653BCPZ-125 | IF Diversity Receiver |
| AD6653BCPZ-150 | IF Diversity Receiver |
| AD6655BCPZ-1251 | IF Diversity Receiver |
| AD6655 | IF Diversity Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653-125EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653 |
| AD6653-150EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk |
| AD6653BCPZ-125 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
| AD6654 | 制造商:Analog Devices 功能描述:- Bulk |
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