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參數(shù)資料
| 型號： | AD7674ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 800KSPS 48-LQFP T/R |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 800k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 138mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7674CBZ-ND - BOARD EVALUATION FOR AD7674 |
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AD7674
Rev. A | Page 23 of 28
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7674 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that only toggles when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read after
Conversion
Though maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 42 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. Data is shifted out MSB first with 18 clock pulses,
and is valid on the rising and falling edge of the clock.
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Also, data can be read at speeds up to 40 MHz, accommodating
both slow digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7674 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 44. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
SCLK
SDOUT
D17
D16
D1
D0
D15
X17
X16
X15
X1
X0
Y17
Y16
BUSY
SDIN
INVSCLK = 0
X17
X16
X
12
3
16
17
18
19
20
EXT/INT = 1
RD = 0
t35
t36 t37
t31
t32
t34
t16
t33
CS
03083-0-042
Figure 42. Slave Serial Data Timing for Reading (Read after Convert)
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| AD7675ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LFCSP EP |
| AD7675ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
| AD7675ACPZ | 功能描述:IC ADC 16BIT SAR 100KSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7675ACPZRL | 功能描述:IC ADC 16BIT SAR 100KSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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