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參數(shù)資料
| 型號(hào)： | AD7674ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 27/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 800KSPS 48-LQFP T/R |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 800k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 138mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7674CBZ-ND - BOARD EVALUATION FOR AD7674 |
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AD7674
Rev. A | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
D
6
/E
X
T
/IN
T
D
7
/I
N
VS
YN
C
D
8
/IN
V
S
C
L
K
D9/
RDC/
S
D
IN
OGN
D
OV
D
DV
DD
DG
ND
D10/
S
D
O
U
T
D1
1
/S
C
L
K
D12/
S
Y
N
C
D13/
R
D
E
RRO
R
48
47
46
45
44
43
42
41
40
39
38
37
PD
B
U
F
AV
D
RE
F
BUF
IN
NC
AG
ND
IN
+
NC
IN
–
RE
F
G
ND
RE
F
1
2
3
4
5
6
7
8
9
10
11
12
AGND
AVDD
MODE0
MODE1
D0/OB/2C
WARP
IMPULSE
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
D5/DIVSCLK[1]
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION
IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES HOWEVER, FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO THE ANALOG GROUND OF THE SYSTEM.
CNVST
PD
RESET
CS
RD
DGND
BUSY
D17
D16
D15
D14
35
AGND
36
34
33
32
31
30
29
28
27
26
25
AD7674
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
03
08
3-
00
4
Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 44
AGND
P
Analog Power Ground Pin.
2, 47
AVDD
P
Input Analog Power Pins. Nominally 5 V.
3
MODE0
DI
Data Output Interface Mode Selection.
4
MODE1
DI
Data Output Interface Mode Selection:
Interface MODE
#
MODE1
MODE0
Description
0
18-Bit
Interface
1
0
1
16-Bit
Interface
2
1
0
Byte Interface
3
1
Serial Interface
5
D0/OB/2C
DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted,
resulting in a twos complement output from its internal shift register.
6
WARP
DI
Conversion Mode Selection. When this input is HIGH and the IMPULSE pin is LOW, WARP selects the
fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the
minimum conversion rate.
7
IMPULSE
DI
Conversion Mode Selection. When this input is HIGH and the WARP pin is LOW, IMPULSE selects a
reduced power mode. In this mode, the power dissipation is approximately proportional to the
sampling rate. When WARP and IMPULSE pins are LOW, the NORMAL mode is selected.
8
D1/A0
DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other
modes, this input pin controls the form in which data is output, as shown in Table 7.
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