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參數(shù)資料
| 型號(hào)： | AD7762BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 625KSPS 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 625k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 958mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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AD7762
Data Sheet
Rev. A | Page 14 of 28
AD7762 INTERFACE
READING DATA
The AD7762 uses a 16-bit bidirectional parallel interface. This
interface is controlled by the RD/WR and CS pins.
When a new conversion result is available, an active low pulse is
output on the DRDY pin. To read a conversion result from the
AD7762, two 16-bit read operations are performed. The DRDY
pulse indicates that a new conversion result is available. Both
RD/WR and CS go low to perform the first read operation.
Shortly after both these lines go low, the data bus becomes
active and the 16 most significant bits (MSBs) of the conversion
result are output. The RD/WR and CS lines must return high
for a full ICLK period before the second read is performed. This
second read contains the 8 least significant bits (LSBs) of the
conversion result along with 6 status bits. These status bits are
shown in Table 7. Descriptions of the other status bits are in
Table 7. Status Bits During Data Read
D7
D0
DValid
Ovr
UFilt
LPwr
FiltOk
DLOk
0
Shortly after RD/WR and CS return high, the data bus returns
to a high impedance state. Both read operations must be
completed before a new conversion result is available because
the new result overwrites the contents on the output register.
If a DRDY pulse occurs during a read operation, the data read
is invalid.
SHARING THE PARALLEL BUS
By its nature, the high accuracy of the AD7762 makes it
sensitive to external noise sources. These include digital activity
on the parallel bus. For this reason, it is recommended that the
AD7762 data lines are isolated from the system data bus by
means of a latch or buffer to ensure that there is no digital
activity on the D0 to D15 pins that is not controlled by the
properly distributed common MCLK signal exist in a system,
these parts can share a common bus without being isolated
from each other. This bus can then be isolated from the system
bus by a single latch or buffer.
WRITING TO THE AD7762
While the AD7762 is configured to convert analog signals with
the default settings on reset, there are many features and
parameters on this part that the user can change by writing to
the device. Because some of the programmable registers are
16 bits wide, two write operations are required to program a
register. The first write contains the register address while the
second write contains the register data. An exception is when a
user filter is being downloaded to the AD7762. This is
described in detail in the Downloading a User-Defined Filter
section. The AD7762 Registers section contains the register
addresses and more details.
line is held high while the CS line is brought low for a minimum
of 4 ICLK periods. The register address is latched during this
period. The CS line is brought high again for a minimum of
4 ICLK periods before the register data is put onto the data bus.
If a read operation occurs between the writing of the register
address and the register data, the register address is cleared and
the next write must be the register address again. This also
provides a method to get back to a known situation if the user
forgets whether the next write is an address or data.
Generally, the AD7762 is written to and configured on power-
up and very infrequently, if at all, after that. Following any write
operation, the full group delay of the filter must pass before
valid data is output from the AD7762.
READING STATUS AND OTHER REGISTERS
The AD7762 features a number of programmable registers. To
read back the contents of these registers or the status register, the
user must first write to the control register of the device, setting
a bit corresponding to the register to be read. The next read
operation outputs the contents of the selected register instead
of a conversion result. The AD7762 Registers section provides
more information on the relevant bits in the control register.
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| AD7762BSVZ-REEL | 功能描述:IC ADC 24BIT 625KSPS 64TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7763 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7763BCP | 制造商:Analog Devices 功能描述:2.5MSPS 18/20 BIT SIGMA DELTA ADC - Bulk |
| AD7763BCPZ | 制造商:Analog Devices 功能描述:2.5MSPS 18/20 BIT SIGMA DELTA ADC - Bulk |
| AD7763BSVZ | 功能描述:IC ADC 24BIT SRL 625KSPS 64TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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