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參數(shù)資料
型號: AD7762BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 9/29頁
文件大?。?/td> 0K
描述: IC ADC 24BIT 625KSPS 64TQFP
標準包裝: 1
位數(shù): 24
采樣率(每秒): 625k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 958mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應商設備封裝: 64-TQFP-EP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
AD7762
Data Sheet
Rev. A | Page 16 of 28
DRIVING THE AD7762
The AD7762 has an on-chip differential amplifier that operates
with a supply voltage (AVDD3) from 3.15 V to 5.25 V. For a
4.096 V reference, the supply voltage must be 5 V.
To achieve the specified performance in normal mode, the
differential amplifier should be configured as a first-order
antialias filter, as shown in Figure 25. Any additional filtering
should be carried out in previous stages using low noise, high
performance op amps, such as the AD8021.
Suitable component values for the first-order filter are listed in
Table 8. The values in Table 8 yield a 10 dB attenuation at the
first alias point of 19 MHz.
04975-040
A1
RIN
RFB
CFB
RIN
RM
CS
RFB
CFB
VIN
A
B
VIN+
Figure 25. Differential Amplifier Configuration
Table 8. Normal Mode Component Values
VREF
RIN
RFB
RM
CS
CFB
4.096 V
1 kΩ
655 Ω
18 Ω
5.6 pF
33 pF
Figure 26 shows the signal conditioning that occurs using the
circuit in Figure 25 with a ±2.5 V input signal biased around
ground and having the component values and conditions in
Table 8. The differential amplifier always biases the output
signal to sit on the optimum common mode of VREF/2, in this
case 2.048 V. The signal is also scaled to give the maximum
allowable voltage swing with this reference value. This is
calculated as 80% of VREF, that is, 0.8 × 4.096 V
≈ 3.275 V p-p
on each input.
To obtain maximum performance from the AD7762, it is
advisable to drive the ADC with differential signals. Figure 27
shows how a bipolar, single-ended signal biased around ground
can drive the AD7762 with the use of an external op amp, such
as the AD8021.
With a 4.096 V reference, a 5 V supply must be provided to the
reference buffer (AVDD4). With a 2.5 V reference, a 3.3 V supply
must be provided to AVDD4.
04975-041
+2.5V
0V
–2.5V
+2.5V
0V
–2.5V
+3.685V
+2.048V
+0.410V
+3.685V
+2.048V
+0.410V
A
VIN+
VIN
B
Figure 26. Differential Amplifier Signal Conditioning
04975-042
A1
RIN
RFB
CFB
RIN
RM
CS
RFB
CFB
VIN
VIN
VIN+
AD8021
2R
R
Figure 27. Single-Ended-to-Differential Conversion
05477-043
CS2
CPB2
SS4
SH4
CPA
SS2
SH2
CS1
CPB1
SS3
SH3
SS1
SH1
ANALOG
MODULATOR
VIN+
Figure 28. Equivalent Input Circuit
The AD7762 employs a double sampling front end, as shown in
Figure 28. For simplicity, only the equivalent input circuit for VIN+
is shown. The equivalent input circuitry for VIN is the same.
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