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參數(shù)資料
| 型號： | AD9148BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QD 1GSPS 196CSPBGA |
| 標準包裝： | 1,500 |
| 系列： | TxDAC+® |
| 設置時間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 2.22W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA，CSPBGA |
| 供應商設備封裝： | 196-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9148
Data Sheet
Rev. B | Page 50 of 72
DIGITAL DATA PATH
The block diagram in Figure 60 shows the functionality of the
complex digital data path. The digital processing includes a
premodulation block, a programmable complex filter, three
half-band interpolation filters with built-in coarse modulation,
a quadrature modulator with a fine resolution NCO as well as
phase, gain, and offset adjustment blocks.
HB2
PREMOD
fS/2
HB1
HB3
DIGITAL
PHASE/GAIN/
OFFSET ADJ
PROG
SINC–1
FILTER
08910-
059
Figure 60. Block Diagram of Digital Data Path
There are two complex digital data paths that feed the four DACs.
Each digital data path accepts I and Q data streams and processes
them as a quadrature data stream, resulting in two quadrature
data streams. All of the signal processing blocks can be used
when the input data stream is represented as complex data.
The data path can be used to process an input data stream
representing four independent real data streams as well; however,
the functionality is somewhat restricted. The premodulation
block can be used, as well as any of the nonshifted interpolation
filter modes.
PREMODULATION
The half-band interpolation filters have selectable pass bands
that allow the center frequencies to be moved in increments
of of their input data rate. The premodulation block provides
a digital upconversion of the incoming waveform by of
the incoming data rate, fDATA. Functionally, the premodulation
multiplies the incoming data samples alternatively by +1 and 1.
This can be used to frequency shift baseband input data to the
center of the interpolation filters pass band.
PROGRAMMABLE INVERSE SINC FILTER
The AD9148 provides a programmable inverse sinc filter to
compensate the DAC roll-off over frequency. Because this filter
is implemented before the interpolation filter, its coefficients
must be changed depending on the interpolation rate and DAC
output center frequency.
Filter Structure
The programmable inverse sinc filter is a nine-tap complex FIR
filter using complex conjugate coefficients. The z-transfer
function is
( )
8
0
7
1
6
2
5
3
4
3
2
1
0
×
+
×
+
×
+
×
+
×
+
×
+
×
+
×
+
=
×
+
=
×
+
×
+
=
z
c
z
c
z
c
z
c
z
c
z
c
z
c
z
c
H
j
H
x
j
x
y
j
y
z
H
Q
I
Q
I
Q
I
where:
xI and xQ are the in-phase (real) and quadrature (imaginary)
filter input, respectively.
yI and yQ are the in-phase (real) and quadrature (imaginary)
filter output, respectively.
HI and HQ are the in-phase (real) and quadrature (imaginary)
filter coefficients, respectively.
c0, c1, c2, c3, and c4 are the complex filter coefficient, and cX their
complex conjugate.
The filter coefficients must be calculated and programmed into
the AD9148 registers to perform the operation desired.
Filter Implementation
To perform the complex filtering of the complex input, the filter
is divided in four filters working in parallel, two sets of HI and
(
) (
)
(
)
Q
I
Q
I
Q
i
Q
I
Q
I
x
H
x
H
j
x
H
x
H
x
j
x
H
j
H
y
j
y
×
+
×
+
×
×
=
×
+
×
+
=
×
+
XI
HI
HQ
YI
YQ
XQ
HI
HQ
+
–
+
08910-
060
Figure 61. Complex Filter Implementation
The coefficients for the filter are stored in SPI Register 0x20 to
Register 0x27 in twos-complement format. They have variable
length, three bits to 10 bits.
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| AD9148BBPZ | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9148BBPZRL | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9148BPCZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148BPCZRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
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