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參數(shù)資料
| 型號： | AD9148BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/72頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT QD 1GSPS 196CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 2.22W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電流，單極 |
| 采樣率（每秒）： | 1G |
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Data Sheet
AD9148
Rev. B | Page 61 of 72
In addition, the P or N output can act as a current source or a
current sink. When sourcing current, the output compliance
voltage is 0 V to 1.6 V. When sinking current, the output compliance
voltage is 0.8 V to 1.6 V. The auxiliary DAC current direction is
programmable via Bit 6, Register 0x33 and Bit 6, Register 0x37
(DAC SPI select is 0 to control AUX1 and AUX2, and DAC SPI
select is 1 to control AUX3 and AUX4). The choice of sinking or
sourcing should be made at circuit design time. There is no
advantage to switching between sourcing and sinking current
after the circuit is in place.
These auxiliary DACs can be used for local oscillator (LO)
cancellation when the DAC output is followed by a quadrature
modulator. More information and example application circuits
are given in the Interfacing to Modulators section.
INTERFACING TO MODULATORS
The AD9148 interfaces to the ADL537x family with a minimal
number of components. An example of the recommended
interface circuitry is shown in Figure 81.
RBIP
50
RBIN
50
IBBN
IBBP
AD9148
ADL537x
RBQN
50
RBQP
50
RLI
100
RLQ
100
IOUT1_N
IOUT1_P
IOUT2_P
IOUT2_N
QBBP
QBBN
08910-
079
Figure 81. Typical Interface Circuitry Between the AD9148 and ADL537x
Family of Modulators
The baseband inputs of the ADL537x family require a dc bias
of 500 mV. The nominal midscale output current on each output
of the DAC is 10 mA (1/2 the full-scale current). Therefore, a
single 50 resistor to ground from each of the DAC outputs
results in the desired 500 mV dc common-mode bias for the
inputs to the ADL537x. The signal level can be reduced by the
addition of the load resistor in parallel with the modulator inputs
(RLI, RLQ). The peak-to-peak voltage swing of the transmitted
signal is
[
]
[
]
L
B
L
B
FS
SIGNAL
R
I
V
+
×
=
2
Baseband Filter Implementation
Most applications require a baseband anti-imaging filter between
the DAC and modulator to filter out Nyquist images and broadband
DAC noise. The filter can be inserted between the I-to-V resistors
at the DAC output and the signal level setting resistor across the
modulator input. Doing this establishes the input and output
impedances for the filter.
Figure 83 shows a fifth-order low-pass filter. A common-mode
choke is used between the I-to-V resistors and the remainder
of the filter. This removes the common-mode signal produced
by the DAC and prevents the common-mode signal from being
converted to a differential signal, which would appear as unwanted
spurious signals in the output spectrum. The common-mode
choke or balun may not be needed if the layout between the
DAC and IQ modulator is optimized and balanced. Splitting
the second filter capacitor into two and grounding the center
point creates a common-mode low-pass filter, providing additional
common-mode rejection of high frequency signals. A purely
differential filter passes common-mode signals.
Driving the ADL5375-15 with the AD9148
The ADL5375-15 requires a 1500 mV dc bias and therefore
requires a slightly more complex interface than most other
Analog Devices, Inc., modulators. It is necessary to level shift
the DAC output from a 500 mV dc bias to the 1500 mV dc bias
that the ADL5375-15 requires. Level shifting can be achieved
with a purely passive network, as shown in Figure 82. In this
network, the dc bias of the DAC remains at 500 mV, while the
input to the ADL5375-15 is 1500 mV. Note that this passive
level shifting network introduces approximately 2 dB of loss
in the ac signal.
IBBN
IBBP
AD9148
ADL5375-15
RBIP
45.3
RBIN
45.3
RBQN
45.3
RBQP
45.3
RLIP
3480
RLIN
3480
RLQN
3480
RLQP
3480
IOUT1_N
IOUT1_P
IOUT2_P
IOUT2_N
QBBP
QBBN
RSIN
1k
RSIP
1k
RSQN
1k
RSQP
1k
5V
08910-
081
Figure 82. Passive Level Shifting Network for Biasing
the ADL5375-15 from the AD9148
IDAC
OR
QDAC
50
MABACT0043
(OPTIONAL)
33nH
2pF
56nH
100
6pF
3pF
22pF
ADL537x
08910-
080
Figure 83. DAC Modulator Interface with Fifth-Order, Low Pass Filter
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9148BBPZ | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9148BBPZRL | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9148BPCZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148BPCZRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148-EBZ | 功能描述:BOARD EVALUATION FOR AD9148 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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