參數(shù)資料
型號(hào): AD9212-65EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/56頁(yè)
文件大小: 0K
描述: BOARD EVALUATION FOR AD9212
設(shè)計(jì)資源: AD9212/22/52 Gerber Files
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 8
位數(shù): 10
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 100mW @ 65MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9212
已供物品: 板,電源
AD9212
Data Sheet
Rev. E | Page 26 of 56
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–1.5ns
–0.5ns
0ns
0.5ns
1.0ns
1.5ns
EY
E
D
IA
G
R
AM
V
O
L
T
A
G
E
(
m
V
)
EYE: ALL BITS
ULS: 12071/12071
90
50
10
20
30
40
60
70
80
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(
H
it
s)
05
96
8-03
0
Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less Than 24 Inches on Standard FR-4
60
80
90
70
50
40
20
10
100
30
0
–200ps
–100ps
100ps
0ps
200ps
T
IE
J
IT
T
ER
HI
ST
O
G
R
A
M
(
H
it
s)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–0.5ns
0ns
0.5ns
1.5ns
–1.5ns
1.0ns
EY
E
D
IAG
R
A
M
VO
L
T
AG
E
(
m
V
)
EYE: ALL BITS
ULS: 12067/12067
0
5968
-028
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4
400
300
200
100
–400
–300
–200
–100
0
–0.5ns
0ns
0.5ns
E
Y
E
DI
AG
RA
M
V
O
L
T
AG
E
(
m
V
)
EYE: ALL BITS
ULS: 12072/12072
80
50
10
20
30
40
60
70
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(
H
it
s)
–1.0ns
1.5ns
–1.5ns
1.0ns
05
96
8-02
9
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D9 ... D0)
1023
+1.00
11 1111 1111
512
0.00
10 0000 0000
511
0.001953
01 1111 1111
0
1.00
00 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 10 bits
times the sample clock rate, with a maximum of 650 Mbps
(10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
information about enabling this feature.
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