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參數(shù)資料
| 型號： | AD9212-65EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9212 |
| 設計資源： | AD9212/22/52 Gerber Files |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 8 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標準）： | 100mW @ 65MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9212 |
| 已供物品： | 板，電源 |
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AD9212
Data Sheet
Rev. E | Page 36 of 56
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9212 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9212, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These capacitors should be located close to the
point of entry at the PC board level and close to the parts, with
minimal trace lengths.
A single PC board ground plane should be sufficient when
using the AD9212. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9212. An
exposed continuous copper plane on the PCB should mate to
the AD9212 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
multiple tie points between the ADC and PCB during the
reflow process, whereas using one continuous plane with no
partitions guarantees only one tie point. See Figure 69 for a PCB
layout example. For detailed information on packaging and the
PCB layout of chip scale packages, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
SILKSCREEN PARTITION
PIN 1 INDICATOR
05
96
8-
03
4
Figure 69. Typical PCB Layout
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