參數(shù)資料
型號(hào): AD9212-65EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 54/56頁(yè)
文件大小: 0K
描述: BOARD EVALUATION FOR AD9212
設(shè)計(jì)資源: AD9212/22/52 Gerber Files
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 8
位數(shù): 10
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 100mW @ 65MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9212
已供物品: 板,電源
Data Sheet
AD9212
Rev. E | Page 7 of 56
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 4.
AD9212-40
AD9212-65
Parameter1
Temp
Min
Typ
Max
Min
Typ
Max
Unit
Maximum Clock Rate
Full
40
65
MSPS
Minimum Clock Rate
Full
10
MSPS
Clock Pulse Width High (tEH)
Full
12.5
7.7
ns
Clock Pulse Width Low (tEL)
Full
12.5
7.7
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
1.5
2.3
3.1
1.5
2.3
3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
1.5
2.3
3.1
1.5
2.3
3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO +
(tSAMPLE/20)
tFCO +
(tSAMPLE/20)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/20) 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
(tSAMPLE/20) 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/20) 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
(tSAMPLE/20) 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
Data-to-Data Skew
(tDATA-MAX tDATA-MIN)
Full
±50
±200
±50
±200
ps
Wake-Up Time (Standby)
25°C
600
ns
Wake-Up Time (Power-Down)
25°C
375
μs
Pipeline Latency
Full
8
CLK
cycles
APERTURE
Aperture Delay (tA)
25°C
750
ps
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
Out-of-Range Recovery Time
25°C
1
CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI interface.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
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