參數(shù)資料
型號: AD9212-65EBZ
廠商: Analog Devices Inc
文件頁數(shù): 28/56頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9212
設計資源: AD9212/22/52 Gerber Files
標準包裝: 1
ADC 的數(shù)量: 8
位數(shù): 10
采樣率(每秒): 65M
數(shù)據接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標準): 100mW @ 65MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9212
已供物品: 板,電源
AD9212
Data Sheet
Rev. E | Page 34 of 56
Table 16. Memory Map Register1
Addr.
(Hex)
Parameter Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Notes/
Comments
Chip Configuration Registers
00
chip_port_config
0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0
0x18
The nibbles
should be
mirrored so
that LSB- or
MSB-first mode
is set correctly
regardless of
shift mode.
01
chip_id
10-bit Chip ID Bits [7:0]
(AD9212 = 0x08), (default)
Read
only
Default is unique
chip ID, different
for each device.
This is a read-
only register.
02
chip_grade
X
Child ID [6:4]
(identify device variants of Chip ID)
000 = 65 MSPS
001 = 40 MSPS
X
Read
only
Child ID used to
differentiate
graded devices.
Device Index and Transfer Registers
04
device_index_2
X
Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
E
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
05
device_index_1
X
Clock
Channel
DCO
1 = on
0 = off
(default)
Clock
Channel
FCO
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
FF
device_update
X
SW
transfer
1 = on
0 = off
(default)
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions Registers
08
modes
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
0x00
Determines
various generic
modes of chip
operation.
09
clock
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01
Turns the
internal duty
cycle stabilizer
on and off.
0D
test_io
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
0x00
When this register
is set, the test
data is placed on
the output pins
in place of
normal data.
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