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參數(shù)資料
| 型號： | AD9277-50EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/48頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9277 |
| 設(shè)計(jì)資源： | AD9276/77 Eval Brd Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 10M ~ 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 733 mVpp |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9277 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9277BSVZ-ND - IC ADC 14BIT LNA/VGA/AAF 100TQFP |
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AD9277
Rev. 0 | Page 39 of 48
SERIAL PORT INTERFACE (SPI)
The AD9277 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. The SPI
offers the user added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the Analog Devices, Inc., AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Three pins define the serial port interface, or SPI: SCLK, SDIO,
and CSB (see Table 16). The SCLK (serial clock) pin is used to
synchronize the read and write data presented to the device. The
SDIO (serial data input/output) pin is a dual-purpose pin that
allows data to be sent to and read from the internal memory map
registers of the device. The CSB (chip select bar) pin is an active
low control that enables or disables the read and write cycles.
Table 16. Serial Port Pins
Pin
Function
SCLK
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
Serial data input/output. Dual-purpose pin that
typically serves as an input or an output, depending
on the instruction sent and the relative position in
the timing frame.
CSB
Chip select bar (active low). This control gates the
read and write cycles.
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its defini-
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
SDIO
SCLK
CSB
tS
tDH
tHIGH
tCLK
tLOW
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
08
18
1-
07
2
Figure 76. Serial Timing Details
Table 17. Serial Timing Definitions
Parameter
Timing (ns min)
Description
tDS
5
Setup time between the data and the rising edge of SCLK
tDH
2
Hold time between the data and the rising edge of SCLK
tCLK
40
Period of the clock
tS
5
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHIGH
16
Minimum period that SCLK should be in a logic high state
tLOW
16
Minimum period that SCLK should be in a logic low state
tEN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 76)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 76)
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