參數(shù)資料
型號(hào)： AD9627-125EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/76頁(yè)
文件大?。?/td> 0K
描述： IC A/D 12BIT 125MSPS DL EVAL BRD
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 12
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 900mW @ 125MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9627
已供物品： 板，電源
12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9627
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007–2010 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @ 125 MSPS
SFDR = 85 dBc to 70 MHz @ 125 MSPS
Low power: 750 mW @ 125 MSPS
SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, WCDMA,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
06571-
001
VIN+A
VIN–A
VREF
SENSE
VIN–B
VIN+B
D11A
D0A
CLK+
CLK–
DCOA
DCOB
D11B
D0B
AGND
SYNC
FD(0:3)B
ADC
SIGNAL MONITOR
DATA
AVDD DVDD
FD(0:3)A
DRGND
PROGRAMMING DATA
DRVDD
FD BITS/THRESHOLD
DETECT
REF
SELECT
DUTY CYCLE
STABILIZER
MULTICHIP
SYNC
FD BITS/THRESHOLD
DETECT
SIGNAL MONITOR
INTERFACE
DCO
GENERATION
DIVIDE
1 TO 8
SIGNAL
MONITOR
SPI
CM
O
S
OU
T
P
U
T
B
U
FFE
R
CM
O
S
O
UT
P
UT
BUF
F
E
R
SHA
CSB
SCLK/
DFS
SDIO/
DCS
CML
RBIAS
SMI
SDO/
OEB
SMI
SCLK/
PDWN
SMI
SDFS
AD9627
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1.
Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/
150 MSPS ADC.
2.
Fast overrange detect and signal monitor with serial output.
3.
Signal monitor block with dedicated serial output mode.
4.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
5.
Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
7.
Pin compatibility with the AD9640, AD9627-11, and AD9600
for a simple migration from 12 bits to 14 bits, 11 bits, or
10 bits.
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