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參數(shù)資料
| 型號(hào)： | AD9510BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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Data Sheet
AD9510
Rev. B | Page 53 of 56
POWER SUPPLY
tables in the Specifications section give the performance expected
from the AD9510 with the power supply voltage within this
range. The absolute maximum range of 0.3 V +3.6 V, with
respect to GND, must never be exceeded on the VS pin.
Follow good engineering practice in the layout of power supply
traces and the ground plane of the printed circuit board (PCB).
Bypass the power supply on the PCB with adequate capacitance
(>10 F). Bypass the AD9510 with adequate capacitors (0.1 F)
at all power pins as close as possible to the part. The layout of the
AD9510-VCO/PCBZ) is a good example.
The AD9510 is a complex part that is programmed for its desired
operating configuration by on-chip registers. These registers are
not maintained over a shutdown of external power. This means
that the registers can lose their programmed values if VS is lost
long enough for the internal voltages to collapse. Careful bypassing
protects the part from memory loss under normal conditions.
Nonetheless, it is important that the VS power supply not become
intermittent, or the AD9510 risks losing its programming.
CPRSET resistors. These resistors must be as close as possible to
the values given as conditions in the Specifications section
(RSET = 4.12 k and CPRSET = 5.1 k). These values are standard
1% resistor values, and are readily obtainable. The bias currents
set by these resistors determine the logic levels and operating
conditions of the internal blocks of the AD9510. The performance
figures given in the Specifications section assume that these
resistor values are used.
The VCP pin is the supply pin for the charge pump (CP). The
voltage at this pin (VCP) can be from VS up to 5.5 V, as required
to match the tuning voltage range of a specific VCO/VCXO.
This voltage must never exceed the absolute maximum of 6 V.
Additionally, never allow VCP to be less than 0.3 V below VS or
GND, whichever is lower.
The exposed metal paddle on the AD9510 package is an electrical
connection, as well as a thermal enhancement. For the device
to function properly, the paddle must be properly attached to
ground (GND). The PCB acts as a heat sink for the AD9510;
therefore, this GND connection must provide a good thermal path
to a larger dissipation area, such as a ground plane on the PCB.
or AD9510-VCO/PCBZ) for a good example.
POWER MANAGEMENT
The power usage of the AD9510 can be managed to use only the
power required for the functions being used. Unused features
and circuitry can be powered down to save power. The following
circuit blocks can be powered down, or are powered down when
not selected (see the Register Map and Description section):
The PLL section can be powered down if not needed.
Any of the dividers are powered down when bypassed—
equivalent to divide-by-one.
The adjustable delay blocks on OUT5 and OUT6 are
powered down when not selected.
Any output can be powered down. However, LVPECL
outputs have both a safe and an off condition. When the
LVPECL output is terminated, use only the safe shutdown
to protect the LVPECL output devices. This still consumes
some power.
The entire distribution section can be powered down when
not needed.
Powering down a functional block does not cause the program-
ming information for that block (in the registers) to be lost.
This means that blocks can be powered on and off without
otherwise having to reprogram the AD9510. However, synchro-
nization is lost. A SYNC must be issued to resynchronize (see
the Single-Chip Synchronization section).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9511 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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