參數資料
型號： AD9510BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數： 54/56頁
文件大?。?/td> 0K
描述： IC CLOCK DIST 8OUT PLL 64LFCSP
標準包裝： 750
類型： 扇出緩沖器（分配），除法器
PLL： 是
輸入： 時鐘
輸出： CMOS，LVDS，LVPECL
電路數： 1
比率 - 輸入:輸出： 2:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.2GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
配用： AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510
AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510
Data Sheet
AD9510
Rev. B | Page 7 of 56
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
PROPAGATION DELAY, CLK-TO-LVDS OUT1
tLVDS
Delay off on OUT5 and OUT6
OUT4, OUT5, OUT6, OUT7
Divide = Bypass
0.99
1.33
1.59
ns
Divide = 2 32
1.04
1.38
1.64
ns
Variation with Temperature
0.9
ps/°C
OUTPUT SKEW, LVDS OUTPUTS
Delay off on OUT5 and OUT6
OUT4 to OUT7 on Same Part2
tSKV
85
+270
ps
OUT5 to OUT6 on Same Part2
tSKV
175
+155
ps
All LVDS OUTs on Same Part2
tSKV
175
+270
ps
All LVDS OUTs Across Multiple Parts3
tSKV_AB
450
ps
Same LVDS OUT Across Multiple Parts3
tSKV_AB
325
ps
CMOS
B outputs are inverted, termination = open
Output Rise Time
tRC
681
865
ps
20% to 80%; CLOAD = 3 pF
Output Fall Time
tFC
646
992
ps
80% to 20%; CLOAD = 3 pF
PROPAGATION DELAY, CLK-TO-CMOS OUT1
tCMOS
Delay off on OUT5 and OUT6
Divide = Bypass
1.02
1.39
1.71
ns
Divide = 2 32
1.07
1.44
1.76
ns
Variation with Temperature
1
ps/°C
OUTPUT SKEW, CMOS OUTPUTS
Delay off on OUT5 and OUT6
All CMOS OUTs on Same Part2
tSKC
140
+145
+300
ps
All CMOS OUTs Across Multiple Parts3
tSKC_AB
650
ps
Same CMOS OUT Across Multiple Parts3
tSKC_AB
500
ps
LVPECL-TO-LVDS OUT
Everything the same; different logic type
Output Skew
tSKP_V
0.74
0.92
1.14
ns
LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT
Everything the same; different logic type
Output Skew
tSKP_C
0.88
1.14
1.43
ns
LVPECL to CMOS on same part
LVDS-TO-CMOS OUT
Everything the same; different logic type
Output Skew
tSKV_C
158
353
506
ps
LVDS to CMOS on same part
DELAY ADJUST4
OUT5 (OUT6); LVDS and CMOS
Shortest Delay Range5
Register 0x35, Register 0x39[5:1] = 11111b
Zero Scale
0.05
0.36
0.68
ns
Register 0x36, Register 0x3A[5:1] = 00000b
Full Scale
0.57
0.95
1.32
ns
Register 0x36, Register 0x3A[5:1] = 11000b
Linearity, DNL
0.5
LSB
Linearity, INL
0.8
LSB
Longest Delay Range5
Register 0x35, Register 0x39[5:1] = 00000b
Zero Scale
0.20
0.57
0.95
ns
Register 0x36, Register 0x3A[5:1] = 00000b
Full Scale
7.0
8.0
9.2
ns
Register 0x36, Register 0x3A[5:1] = 11000b
Linearity, DNL
0.3
LSB
Linearity, INL
0.6
LSB
Delay Variation with Temperature
Long Delay Range, 8 ns6
Zero Scale
0.35
ps/°C
Full Scale
0.14
ps/°C
Short Delay Range, 1 ns6
Zero Scale
0.51
ps/°C
Full Scale
0.67
ps/°C
1
These measurements are for CLK1. For CLK2, add approximately 25 ps.
2
This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.
3
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.
4
The maximum delay that can be used is a little less than one half the period of the clock. A longer delay disables the output.
5
Incremental delay; does not include propagation delay.
6
All delays between zero scale and full scale can be estimated by linear interpolation.
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