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參數(shù)資料
| 型號： | AD9520-3BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2GHZ VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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Data Sheet
AD9520-3
Rev. A | Page 49 of 80
LVPECL Output Drivers
The LVPECL differential voltage (VOD) is selectable (from
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB). The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be set to either 2.5 V or 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
R2
200
R1
200
SW1B
SW1A
SW2
QN2
QN1
N2
N1
OUT
4.4mA
07216-
058
Figure 54. LVPECL Output Simplified Equivalent Circuit
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that causes a dc voltage to
appear at the powered down outputs. However, total power-
down mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting Register 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while powered
down. There are three ways to activate safe power-down mode:
individually set the power-down bit for each driver, power down
an individual output channel (all of the drivers associated with
that channel are powered down automatically), and activate
sleep mode.
CMOS Output Drivers
The user can also individually configure each LVPECL output as a
pair of CMOS outputs, which provides up to 24 CMOS outputs.
When an output is configured as CMOS, CMOS Output A and
CMOS Output B are automatically turned on. For any given
differential pair, either CMOS Output A or CMOS Output B
can be turned on or off independently.
The user can also select the relative polarity of the CMOS outputs
for any combination of inverting and noninverting (refer to
Register 0x0F0 to Register 0x0FB).
OUT1/
OUT1
VS_DRV
07216-
035
Figure 55. CMOS Equivalent Output Circuit
Each CMOS output can be powered down, as needed, to save
power. The CMOS output power-down is individually controlled
by the enable CMOS output bits, Bits[6:5] in Register 0x0F0 to
Register 0x0FB. The CMOS driver is in tristate when it is
powered down.
Note that activating a CMOS driver in the same output channel
group as the LVPECL drivers may cause the LVPECL driver
performance to degrade. In applications where jitter
performance is critical, the user should test the desired
configuration using an evaluation board, and special steps may
need to be taken to ensure the desired performance.
RESET MODES
The AD9520 has a power-on reset (POR) and several other
ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when VS
reaches ~2.6 V (<2.8 V) and restores the chip either to the setting
that is stored in the EEPROM (with the EEPROM pin = 1b) or
to the on-chip setting (with the EEPROM pin = 0b). At power-
on, the AD9520 also executes a SYNC operation approximately
50 ms after the supply reaches ~2.4 V, which brings the outputs
into phase alignment according to the default settings. It takes
~70 ms for the outputs to begin toggling after the power-on
reset pulse signal is internally generated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-3BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9520-4/PCBZ | 功能描述:BOARD EVAL FOR AD9520-4 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9520-4BCPZ | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9520-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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