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參數(shù)資料
| 型號： | AD9520-3BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 69/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2GHZ VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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Data Sheet
AD9520-3
Rev. A | Page 71 of 80
Table 55. Output Driver Control
Reg.
Addr.
(Hex) Bits
Name
Description
0x0F0 7
OUT0 format
Selects the output type for OUT0.
0: LVPECL (default).
1: CMOS.
[6:5]
OUT0 CMOS
configuration
Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1b.
Bits[6:5]
OUT0A
OUT0B
00
01
10
11 (default)
Tristate
On
Tristate
On
Tristate
On
[4:3]
OUT0 polarity
Sets the output polarity for OUT0.
Bit 7
Bit 4
Bit 3
Output Type
OUT0A
OUT0B
0 (default)
0
1
X
0 (default)
0
1
0 (default)
1
0
1
0
1
LVPECL
CMOS
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting Noninverting
Inverting
Noninverting
[2:1]
OUT0 LVPECL
differential
voltage
Sets the LVPECL output differential voltage (VOD).
Bit 2
Bit 1
VOD (mV)
0
1 (default)
1
0
1
0 (default)
1
400
600
780
960
0
OUT0 LVPECL
power-down
LVPECL power-down.
0: normal operation (default).
1: safe power-down.
0x0F1 [7:0]
OUT1 control
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
0x0F2 [7:0]
OUT2 control
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
0x0F3 [7:0]
OUT3 control
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
0x0F4 [7:0]
OUT4 control
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
0x0F5 [7:0]
OUT5 control
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
0x0F6 [7:0]
OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0x0F7 [7:0]
OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0x0F8 [7:0]
OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0x0F9 [7:0]
OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0x0FA [7:0]
OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0x0FB [7:0]
OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0x0FC 7
CSDLD en OUT7
OUT7 is enabled only if the CSDLD signal is high.
Bit 7
CSDLD
Signal
OUT7 Enable Status
0
1
0
1
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enables OUT7 if not powered down by other settings. For this feature, use current
source digital lock detect and set the enable LD pin comparator bit (Register 0x01D[3]).
6
CSDLD en OUT6
OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
5
CSDLD en OUT5
OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
4
CSDLD en OUT4
OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
3
CSDLD en OUT3
OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT2
OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT1
OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT0
OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0x0FD [7:4]
Unused
Unused.
3
CSDLD en OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT9
OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT8
OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-3BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9520-4/PCBZ | 功能描述:BOARD EVAL FOR AD9520-4 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9520-4BCPZ | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9520-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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