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參數(shù)資料
| 型號： | AD9520-4BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 設計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4 |
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AD9520-4
Data Sheet
Rev. A | Page 36 of 80
The differential reference input receiver is powered down when
the differential reference input is not selected or when the PLL
is powered down. The single-ended buffers power down when
the PLL is powered down, or when their respective individual
power down registers are set. When the differential mode is
selected, the single-ended inputs are powered down.
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible
to dc couple to these inputs. If the differential REFIN is driven
by a single-ended signal, the unused side (REFIN) should be
decoupled via a suitable capacitor to a quiet ground. Figure 43
shows the equivalent circuit of REFIN.
VS
REF1
REF2
REFIN
150
10k 12k
10k 10k
REFIN
85k
VS
85k
VS
07217-
066
Figure 43. REFIN Equivalent Circuit for Non-XTAL Mode
Crystal mode is nearly identical to differential mode. The user
enables a maintaining amplifier by setting the enable XTAL
OSC bit, and putting a series resonant, AT fundamental cut
crystal across the REFIN and REFIN pins.
Reference Switchover
The AD9520 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9517 supports automatic revertive and
manual PLL reference clock switching between REF1 (on Pin
REFIN) and REF2 (on Pin REFIN). This feature supports
networking and other applications that require smooth switching
of redundant references. When used in conjunction with the
automatic holdover function, the AD9520 can achieve a worst-
case reference input switchover with an output frequency
disturbance as low as 10 ppm.
The AD9520 features a dc offset option in single-ended mode.
This option is designed to eliminate the risk of the reference
inputs chattering when they are ac-coupled and the reference
clock disappears. When using the reference switchover, the single-
ended reference inputs should be dc-coupled CMOS levels
(with the AD9520 dc offset feature disabled). Alternatively, the
inputs can be ac-coupled and dc offset feature enabled. Keep in
mind, however, that the minimum input amplitude for the
reference inputs is greater when the dc offset is turned on.
Reference switchover can be performed manually or automatically.
Manual switchover is performed either through Register 0x01C
or by using the REF_SEL pin. Manual switchover requires the
presence of a clock on the reference input that is being switched to;
otherwise, the deglitching feature must be disabled in Bit 7 of
Register 0x01C. The reference switching logic fails if this condition
is not met, and the PLL does not reacquire.
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. The STATUS pin can also be used
for this function, and REF2 can be used as the preferred reference.
A switchover deglitch feature ensures that the PLL does not receive
rising edges that are far out of alignment with the newly selected
reference. For the switchover deglitch feature to work correctly,
the presence of a clock is required on the reference input that is
being switched to. The deglitching feature can also be disabled
(Register 0x01C[7]).
Automatic nonrevertive switching is not supported.
Reference Divider R
The reference inputs are routed to the reference divider, R. R is
a 14-bit counter that can be set to any value from 0 to 16,383 by
writing to Register 0x011 and Register 0x012 (both R = 0 and R = 1
give divide-by-1.) The output of the R divider goes to one of the
PFD inputs to be compared with the VCO frequency divided by
the N divider. The frequency applied to the PFD must not exceed
the maximum allowable frequency, which depends on the
antibacklash pulse setting (see Table 2).
The R divider has its own reset. The R divider can be reset using
the shared reset bit of the R, A, and B counters. It can also be
reset by a SYNC operation.
VCO/VCXO Feedback Divider N—P, A, and B
The N divider is a combination of a prescaler, P, and two counters,
A and B. The total divider value is
N = (P × B) + A
where P can be 2, 4, 8, 16, or 32.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| AD9520-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-5BCPZ | 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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