- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9216 > AD9520-4BCPZ (Analog Devices Inc)IC CLOCK GEN 1.6GHZ VCO 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9520-4BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 設計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Data Sheet
AD9520-4
Rev. A | Page 43 of 80
DIVIDE BY 1,
2, 3, 4, 5, OR 6
LF
CLK/CLK
R
DIVIDER
R
DELAY
N
DIVIDER
N
DELAY
PFD
CP
LOOP
FILTER
MUX1
REG 0x01E[1] = 1
0
1
REFIN/
REFIN
MU
X
3
REG 0x01E[2]
ZERO DELAY
INTERNAL FEEDBACK PATH
EXTERNAL FEEDBACK PATH
ZERO DELAY FEEDBACK CLOCK
CHANNEL DIVIDER 0
CHANNEL DIVIDER 1
CHANNEL DIVIDER 2
CHANNEL DIVIDER 3
OUT0 TO OUT2
OUT3 TO OUT5
OUT6 TO OUT8
OUT9 TO OUT11
AD9520
07
217
-05
3
Figure 49. Zero Delay Function
External Zero Delay Mode
The external zero delay function of the AD9520 is achieved by
feeding one clock output back to the CLK input and ultimately
back to the PLL N divider. In Figure 49, the change in signal
routing for external zero delay mode is shown in red.
Set Register 0x01E[2:1] = 11b to select external zero delay mode.
In external zero delay mode, one of the twelve output clocks
(OUT0 to OUT11) can be routed back to the PLL (N divider)
through the CLK/CLK pins and through MUX3 and MUX1.
This feedback path is shown in red in Figure 49.
For VCO calibration to work correctly, the user must specify which
channel divider is used for external zero delay mode. Channel
Divider 0 is the default. Change the value in Register 0x01E[4:3]
to select Channel Divider 1, Channel Divider 2, or Channel
Divider 3 for zero delay feedback.
The PLL synchronizes the phase/edge of the feedback output clock
with the phase/edge of the reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the R delay and the
N delay inside the PLL can be programmed to compensate for
the propagation delay from the PLL components to minimize the
phase offset between the feedback clock and the reference input.
CLOCK DISTRIBUTION
A clock channel consists of three LVPECL clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVPECL or CMOS at the pins.
The AD9520 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer from
1 to 32.
The AD9520 features a VCO divider that divides the VCO output
by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz.
The other is to allow the AD9520 to generate even lower
frequencies than would be possible with only a simple post divider.
External clock signals connected to the CLK input can also use
the VCO divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
相關PDF資料 |
PDF描述 |
|---|---|
| VE-B4T-MW-B1 | CONVERTER MOD DC/DC 6.5V 100W |
| VE-B13-MY-F1 | CONVERTER MOD DC/DC 24V 50W |
| VE-B4H-MV | CONVERTER MOD DC/DC 52V 150W |
| M83723/83W20286 | CONN RCPT 28POS WALL MT W/PINS |
| VE-B43-MW-B1 | CONVERTER MOD DC/DC 24V 100W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-5BCPZ | 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。