參數(shù)資料
型號(hào)： AD9520-4BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 48/80頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 1.6GHZ VCO 64LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.8GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
配用： AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4
AD9520-4
Data Sheet
Rev. A | Page 52 of 80
SDA
MSB
ACKNOWLEDGE FROM
SLAVE-RECEIVER
ACKNOWLEDGE FROM
SLAVE-RECEIVER
SCL
S
P
1
2
8
9
1
2
8
3 TO 7
9
10
07217-
162
Figure 58. Acknowledge Bit
SDA
MSB = 0
ACKNOWLEDGE FROM
SLAVE-RECEIVER
ACKNOWLEDGE FROM
SLAVE-RECEIVER
SCL
S
P
1
2
8
9
1
2
8
3 TO 7
9
10
07217-
163
Figure 59. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
SDA
ACKNOWLEDGE FROM
MASTER-RECEIVER
NO ACKNOWLEDGE
FROM
SLAVE-RECEIVER
SCL
S
P
1
2
8
9
1
2
8
3 TO 7
9
10
07217-
164
MSB = 1
Figure 60. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All IC slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0b = write, 1b = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/W bit is 0b, the
master (transmitter) writes to the slave device (receiver). If the
R/W bit is 1b, the master (receiver) reads from the slave device
(transmitter).
The format for these commands is described in the Data
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (8-bit) from either master (write mode) or
slave (read mode), followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted per
transfer is unrestricted. In write mode, the first two data bytes
immediately after the slave address byte are the internal
memory (control registers) address bytes with the high address
byte first. This addressing scheme gives a memory address up to
216 1 = 65,535. The data bytes after these two memory address
bytes are register data written into the control registers. In read
mode, the data bytes after the slave address byte are register
data read from the control registers.
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts
a stop condition to end data transfer during the (10th) clock pulse
following the acknowledge bit for the last data byte from the slave
device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter) but
does not pull it low during the ninth clock pulse. This is known as
a no acknowledge bit. By receiving the no acknowledge bit, the
slave device knows that the data transfer is finished and releases
the SDA line. The master then takes the data line low during the
low period before the 10th clock pulse, and high during the
10th clock pulse to assert a stop condition.
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time, and partially transferred bytes are discarded.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9520-4BCPZ-REEL7 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-5 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator
AD9520-5/PCBZ 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9520-5BCPZ 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
AD9520-5BCPZ-REEL7 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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