參數(shù)資料
型號(hào)： AD9520-4BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 66/80頁
文件大小： 0K
描述： IC CLOCK GEN 1.6GHZ VCO 64LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.8GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
配用： AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4
Data Sheet
AD9520-4
Rev. A | Page 69 of 80
Reg.
Addr.
(Hex) Bits Name
Description
[4:0] REFMON pin
control
Selects the signal that is connected to the REFMON pin.
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Level or
Dynamic
Signal
Signal at REFMON Pin
0
LVL
Ground, dc (default).
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
1
0
DYN
REF2 clock (N/A in differential mode).
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
0
1
LVL
Status of REF1 frequency; active high.
0
1
0
LVL
Status of REF2 frequency; active high.
0
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
LVL
Status of VCO frequency; active high.
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
0
1
LVL
DLD; active high.
0
1
0
LVL
Holdover active; active high.
0
1
LVL
N/A. Do not use.
1
0
LVL
VS (PLL power supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency; active low.
1
0
LVL
Status of REF2 frequency; active low.
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency; active low.
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
DLD; active low.
1
0
LVL
Holdover active; active low.
1
LVL
N/A. Do not use.
0x01C 7
Disable
switchover
deglitch
Disables or enables the switchover deglitch circuit.
0: enables the switchover deglitch circuit (default).
1: disables the switchover deglitch circuit.
6
Select REF2
If Register 0x01C[5] = 0b, selects the reference for PLL when in manual; register selected reference control.
0: selects REF1 (default).
1: selects REF2.
5
Use REF_SEL pin
If Register 0x01C[4] = 0b (manual), sets the method of PLL reference selection.
0: uses Register 0x01C[6] (default).
1: uses REF_SEL pin.
4
Enable automatic
reference
switchover
Automatic or manual reference switchover. Single-ended reference mode must be selected by Register 0x01C[0] = 0b.
0: manual reference switchover (default).
1: automatic reference switchover. Setting this bit also powers on REF1 and REF2 and overrides the settings in Register 0x01C[2:1].
3
Stay on REF2
Stays on REF2 after switchover.
0: returns to REF1 automatically when REF1 status is good again (default).
1: stays on REF2 after switchover. Does not automatically return to REF1.
2
Enable REF2
This bit turns the REF2 power on. This bit is overridden when automatic reference switchover is enabled.
0: REF2 power off (default).
1: REF2 power on.
1
Enable REF1
This bit turns the REF1 power on. This bit is overridden when automatic reference switchover is enabled.
0: REF1 power off (default).
1: REF1 power on.
0
Enable
differential ref
Selects the PLL reference mode, differential or single-ended. Register 0x01C[2:1] should be cleared when this bit is set.
0: single-ended reference mode (default); 1: differential reference mode.
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