參數(shù)資料
型號(hào)： AD9613-170EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9613-170
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 1.75 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 670mW @ 170MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9613
已供物品： 板
AD9613
Data Sheet
Rev. C | Page 26 of 36
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
offer excellent jitter performance.
10
0
0.1F
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDS DRIVER
ADC
09637-
059
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9613 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
The AD9613 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9613 contains a duty-cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9613.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The
duty cycle control loop does not function for clock rates less
than 40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 s to 5 s is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the period that the
loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fIN) due to jitter (tJ) can be calculated by
SNRHF = 10 log[(2π × fIN × tJRMS)2 + 10
)
10
/
(
LF
SNR
/
]
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
80
75
70
65
60
55
50
1
10
100
1000
INPUT FREQUENCY (MHz)
S
NR
(
d
Bc)
09637-
060
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
Figure 56. AD9613-250 SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9613.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sample Systems and the Effects of Clock Phase Noise and Jitter,
for more information about jitter performance as it relates to
ADCs.
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